Lines Matching defs:Ops
236 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
239 void AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
243 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc);
245 void AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, EVT InactiveTy);
1651 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
1654 MVT::Other, Ops);
1661 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
1664 MVT::Other, Ops);
1692 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)),
1695 MVT::i32, MVT::Other, Ops);
1740 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
1743 MVT::Other, Ops);
1836 SDValue Ops[] = {Base,
1843 N->getValueType(0), MVT::Other, Ops);
1859 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1860 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1870 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1871 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1881 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1882 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1892 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1893 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1906 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1908 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1921 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1923 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1936 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1938 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
2175 SmallVector<SDValue, 7> Ops;
2181 Ops.push_back(MemAddr);
2182 Ops.push_back(Align);
2191 Ops.push_back(Inc);
2195 Ops.push_back(Reg0);
2197 Ops.push_back(Pred);
2198 Ops.push_back(Reg0);
2199 Ops.push_back(Chain);
2200 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2217 Ops.push_back(SDValue(VLdA, 1));
2218 Ops.push_back(Align);
2224 Ops.push_back(Reg0);
2226 Ops.push_back(SDValue(VLdA, 0));
2227 Ops.push_back(Pred);
2228 Ops.push_back(Reg0);
2229 Ops.push_back(Chain);
2230 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
2309 SmallVector<SDValue, 7> Ops;
2340 Ops.push_back(MemAddr);
2341 Ops.push_back(Align);
2350 Ops.push_back(Inc);
2355 Ops.push_back(Reg0);
2357 Ops.push_back(SrcReg);
2358 Ops.push_back(Pred);
2359 Ops.push_back(Reg0);
2360 Ops.push_back(Chain);
2361 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2392 Ops.push_back(SDValue(VStA, 0));
2393 Ops.push_back(Align);
2399 Ops.push_back(Reg0);
2401 Ops.push_back(RegSeq);
2402 Ops.push_back(Pred);
2403 Ops.push_back(Reg0);
2404 Ops.push_back(Chain);
2406 Ops);
2482 SmallVector<SDValue, 8> Ops;
2483 Ops.push_back(MemAddr);
2484 Ops.push_back(Align);
2489 Ops.push_back(IsImmUpdate ? Reg0 : Inc);
2510 Ops.push_back(SuperReg);
2511 Ops.push_back(getI32Imm(Lane, dl));
2512 Ops.push_back(Pred);
2513 Ops.push_back(Reg0);
2514 Ops.push_back(Chain);
2518 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2541 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2543 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
2544 Ops.push_back(PredicateMask);
2545 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2549 void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2552 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
2553 Ops.push_back(PredicateMask);
2554 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2555 Ops.push_back(Inactive);
2559 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) {
2560 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
2561 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2562 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2566 void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
2568 Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
2569 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2570 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
2571 Ops.push_back(SDValue(
2578 SmallVector<SDValue, 8> Ops;
2592 Ops.push_back(N->getOperand(2)); // vector of base addresses
2595 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate offset
2598 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4));
2600 AddEmptyMVEPredicateToOps(Ops, Loc);
2602 Ops.push_back(N->getOperand(0)); // chain
2609 SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), VTs, Ops);
2621 SmallVector<SDValue, 8> Ops;
2624 Ops.push_back(N->getOperand(1));
2625 Ops.push_back(N->getOperand(2));
2630 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count
2632 Ops.push_back(N->getOperand(3));
2639 Ops.push_back(getI32Imm(SatBit, Loc));
2644 Ops.push_back(getAL(CurDAG, Loc));
2645 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2647 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2654 SmallVector<SDValue, 8> Ops;
2660 Ops.push_back(N->getOperand(FirstInputOp));
2661 Ops.push_back(N->getOperand(FirstInputOp + 1));
2670 Ops.push_back(CarryIn);
2675 AddMVEPredicateToOps(Ops, Loc,
2679 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0));
2681 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2686 SmallVector<SDValue, 8> Ops;
2690 Ops.push_back(N->getOperand(1));
2691 Ops.push_back(N->getOperand(2));
2693 Ops.push_back(getI32Imm(ImmValue, Loc)); // immediate shift count
2696 AddMVEPredicateToOps(Ops, Loc, N->getOperand(4));
2698 AddEmptyMVEPredicateToOps(Ops, Loc);
2700 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), ArrayRef(Ops));
2744 SmallVector<SDValue, 8> Ops;
2747 Ops.push_back(N->getOperand(4));
2748 Ops.push_back(N->getOperand(5));
2751 Ops.push_back(N->getOperand(6));
2752 Ops.push_back(N->getOperand(7));
2755 AddMVEPredicateToOps(Ops, Loc, N->getOperand(8));
2757 AddEmptyMVEPredicateToOps(Ops, Loc);
2759 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2821 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2823 CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops);
2831 SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
2833 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);
2867 SmallVector<SDValue, 8> Ops;
2874 Ops.push_back(N->getOperand(OpIdx++)); // base
2876 Ops.push_back(N->getOperand(OpIdx++)); // limit
2880 Ops.push_back(getI32Imm(ImmValue, Loc));
2883 AddMVEPredicateToOps(Ops, Loc, N->getOperand(OpIdx), Inactive);
2885 AddEmptyMVEPredicateToOps(Ops, Loc, N->getValueType(0));
2887 CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), ArrayRef(Ops));
2894 SmallVector<SDValue, 8> Ops;
2901 Ops.push_back(getI32Imm(ImmCoprocVal, Loc));
2910 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, AccLo, AccHi), 0));
2915 Ops.push_back(N->getOperand(OpIdx++));
2920 Ops.push_back(getI32Imm(ImmVal, Loc));
2926 Ops.push_back(Pred);
2927 Ops.push_back(PredReg);
2931 SDNode *InstrNode = CurDAG->getMachineNode(Opcode, Loc, MVT::Untyped, Ops);
3020 SmallVector<SDValue, 6> Ops;
3021 Ops.push_back(MemAddr);
3022 Ops.push_back(Align);
3032 Ops.push_back(Reg0);
3036 Ops.push_back(Inc);
3047 Ops.push_back(SDValue(VLdA, 0));
3051 Ops.push_back(Pred);
3052 Ops.push_back(Reg0);
3053 Ops.push_back(Chain);
3055 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
3245 SmallVector<SDValue, 3> Ops{
3247 AddEmptyMVEPredicateToOps(Ops, SDLoc(N), Type);
3268 ReplaceNode(N, CurDAG->getMachineNode(Opcode, SDLoc(N), Type, Ops));
3305 SmallVector<SDValue, 3> Ops{Node->getOperand(0),
3307 AddEmptyMVEPredicateToOps(Ops, dl, Type);
3309 ReplaceNode(N, CurDAG->getMachineNode(Opcode, dl, Type, Ops));
3373 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3376 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3385 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
3387 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
3392 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3396 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3417 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3421 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3439 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3443 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3460 SDValue Ops[] = { N->getOperand(0).getOperand(0),
3464 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3523 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
3527 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops);
3579 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),
3582 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
3584 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
3587 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
3664 SDValue Ops[] = {ST->getValue(),
3671 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops);
3710 SDValue Ops[] = {
3717 Ops);
3719 SDValue Ops[] = {
3727 Ops);
3763 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
3766 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
3810 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3811 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
3814 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3816 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
3829 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
3830 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
3833 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
3835 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
3872 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3875 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops));
3878 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl),
3882 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops));
3917 SDValue Ops[] = { N0.getOperand(0), Imm16,
3919 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
3928 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
3932 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
3937 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3941 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops));
3944 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3950 MVT::i32, MVT::i32, Ops));
3956 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3960 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops));
3963 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
3969 MVT::i32, MVT::i32, Ops));
3997 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
4000 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
4038 SDValue Ops[] = { N->getOperand(1),
4042 SDNode *New = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
4062 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain};
4064 {MVT::Untyped, MVT::Other}, Ops);
4093 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain};
4094 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops);
4101 SDValue Ops[] = { N->getOperand(1),
4106 CurDAG->getVTList(MVT::i32, MVT::Other), Ops);
4185 SDValue Ops[] = { N1, Tmp2, N3, Chain, InGlue };
4187 MVT::Glue, Ops);
4216 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32),
4219 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
4222 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
4225 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);
4258 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,
4260 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);
4275 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4276 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4287 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4288 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4298 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg};
4299 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops));
4731 SmallVector<SDValue, 5> Ops;
4732 Ops.push_back(getI32Imm(N->getConstantOperandVal(2), dl)); /* coproc */
4733 Ops.push_back(getI32Imm(N->getConstantOperandVal(3), dl)); /* opc */
4734 Ops.push_back(getI32Imm(N->getConstantOperandVal(4), dl)); /* CRm */
4740 Ops.push_back(getAL(CurDAG, dl));
4741 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4744 Ops.push_back(Chain);
4749 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
4773 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl),
4775 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
4826 SmallVector<SDValue, 7> Ops;
4828 Ops.push_back(Val0);
4829 Ops.push_back(Val1);
4832 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
4833 Ops.push_back(MemAddr);
4834 Ops.push_back(getAL(CurDAG, dl));
4835 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
4836 Ops.push_back(Chain);
4842 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
5193 SDValue Ops[] = { Src, Src, Pred, Reg0 };
5194 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops);
5204 SDValue Ops[] = { Src, Pred, Reg0 };
5205 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops);
5373 std::vector<SDValue> &Ops) {
5384 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32));
5496 std::vector<SDValue> Ops;
5497 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
5499 if (!Ops.empty()) {
5506 if (Ops.size() == 5){
5510 assert(Ops.size() == 3 &&
5516 Ops.push_back(getAL(CurDAG, DL));
5517 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
5518 Ops.push_back(N->getOperand(0));
5519 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops));
5527 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
5532 DL, MVT::i32, MVT::Other, Ops));
5557 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5560 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops));
5572 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5576 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops));
5583 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5586 DL, MVT::i32, MVT::Other, Ops));
5591 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
5595 MVT::i32, MVT::Other, Ops));
5611 std::vector<SDValue> Ops;
5612 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
5614 if (!Ops.empty()) {
5620 if (Ops.size() == 5) {
5622 Ops.insert(Ops.begin()+2, N->getOperand(2));
5624 assert(Ops.size() == 3 &&
5628 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2);
5631 Ops.push_back(getAL(CurDAG, DL));
5632 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
5633 Ops.push_back(N->getOperand(0));
5635 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
5642 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
5647 DL, MVT::Other, Ops));
5665 Ops = { N->getOperand(2), getAL(CurDAG, DL),
5667 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops));
5683 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
5686 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops));
5695 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
5699 DL, MVT::Other, Ops));
5809 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
5810 Ops.push_back(T1.getValue(1));
5811 CurDAG->UpdateNodeOperands(GU, Ops);