Lines Matching defs:NumVecs
211 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
214 /// For NumVecs <= 2, QOpcodes1 is not used.
215 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
219 /// SelectVST - Select NEON store intrinsics. NumVecs should
222 /// For NumVecs <= 2, QOpcodes1 is not used.
223 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
227 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
231 unsigned NumVecs, const uint16_t *DOpcodes,
283 /// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
286 /// pointer points to a set of NumVecs sub-opcodes used for the
288 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
305 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
309 unsigned NumVecs, const uint16_t *DOpcodes,
348 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1945 unsigned NumVecs, bool is64BitVector) {
1946 unsigned NumRegs = NumVecs;
1947 if (!is64BitVector && NumVecs < 3)
2110 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
2112 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;
2115 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
2120 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
2133 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
2158 if (NumVecs == 1)
2161 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2178 if (is64BitVector || NumVecs <= 2) {
2185 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
2237 if (NumVecs == 1) {
2248 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2251 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
2253 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
2257 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
2262 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
2278 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
2312 if (is64BitVector || NumVecs <= 2) {
2314 if (NumVecs == 1) {
2320 if (NumVecs == 2)
2326 SDValue V3 = (NumVecs == 3)
2344 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
2377 SDValue V3 = (NumVecs == 3)
2412 unsigned NumVecs,
2416 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2430 unsigned Lane = N->getConstantOperandVal(Vec0Idx + NumVecs);
2435 if (NumVecs != 3) {
2437 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2469 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2488 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2495 if (NumVecs == 2) {
2502 SDValue V3 = (NumVecs == 3)
2531 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2534 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2536 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2791 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,
2812 EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);
2820 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {
2833 CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);
2837 for (i = 0; i < NumVecs; i++)
2954 bool isUpdating, unsigned NumVecs,
2959 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2972 if (NumVecs != 3) {
2974 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
3006 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
3024 : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]
3029 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
3039 if (is64BitVector || NumVecs == 1) {
3062 if (NumVecs == 1) {
3068 for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {
3073 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
3075 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));