Lines Matching defs:NumAlignedDPRCS2Regs

174                         unsigned NumAlignedDPRCS2Regs);
1527                                     unsigned NumAlignedDPRCS2Regs,
1546       if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1605                                    unsigned NumAlignedDPRCS2Regs) const {
1641       if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1712 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1717                                     unsigned NumAlignedDPRCS2Regs,
1731     if (DNum > NumAlignedDPRCS2Regs - 1)
1764       .addImm(8 * NumAlignedDPRCS2Regs)
1787   // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1793   if (NumAlignedDPRCS2Regs >= 6) {
1804     NumAlignedDPRCS2Regs -= 4;
1812   if (NumAlignedDPRCS2Regs >= 4) {
1823     NumAlignedDPRCS2Regs -= 4;
1827   if (NumAlignedDPRCS2Regs >= 2) {
1837     NumAlignedDPRCS2Regs -= 2;
1841   if (NumAlignedDPRCS2Regs) {
1859                         unsigned NumAlignedDPRCS2Regs) {
1867   switch(NumAlignedDPRCS2Regs) {
1885 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1890                                       unsigned NumAlignedDPRCS2Regs,
1921   // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1925   if (NumAlignedDPRCS2Regs >= 6) {
1935     NumAlignedDPRCS2Regs -= 4;
1943   if (NumAlignedDPRCS2Regs >= 4) {
1952     NumAlignedDPRCS2Regs -= 4;
1956   if (NumAlignedDPRCS2Regs >= 2) {
1964     NumAlignedDPRCS2Regs -= 2;
1968   if (NumAlignedDPRCS2Regs)
1991   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
2011                  NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
2020                  NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
2026   if (NumAlignedDPRCS2Regs)
2027     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2041   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
2045   if (NumAlignedDPRCS2Regs)
2046     emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2056                 NumAlignedDPRCS2Regs);
2061                 NumAlignedDPRCS2Regs);