Lines Matching defs:Opc
422 unsigned Opc;
425 Opc = ARM::FCONSTD;
428 Opc = ARM::FCONSTS;
432 TII.get(Opc), DestReg).addImm(Imm));
443 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
447 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
461 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
466 TII.get(Opc), ImmReg)
477 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
482 TII.get(Opc), ImmReg)
545 unsigned Opc;
551 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
553 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
555 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
574 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
575 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
590 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
594 MIMD, TII.get(Opc), NewDestReg)
656 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
659 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
662 TII.get(Opc), ResultReg)
834 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
836 TII.get(Opc), ResultReg)
901 unsigned Opc;
912 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
914 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
917 Opc = ARM::LDRBi12;
919 Opc = ARM::LDRSB;
932 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
934 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
936 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
948 Opc = ARM::t2LDRi8;
950 Opc = ARM::t2LDRi12;
952 Opc = ARM::LDRi12;
962 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
965 Opc = ARM::VLDRS;
977 Opc = ARM::VLDRD;
989 TII.get(Opc), ResultReg);
1050 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1051 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1053 TII.get(Opc), Res)
1324 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1328 TII.get(Opc)).addReg(AddrReg));
1556 unsigned Opc;
1557 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1559 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1564 TII.get(Opc), ResultReg).addReg(FP));
1581 unsigned Opc;
1583 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1585 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1591 TII.get(Opc), ResultReg).addReg(Op));
1744 unsigned Opc;
1748 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1751 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1754 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1770 TII.get(Opc), ResultReg)
1795 unsigned Opc;
1800 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1803 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1806 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1817 TII.get(Opc), ResultReg)
2636 uint32_t Opc : 16;
2642 { // ARM Opc S Shift Imm
2650 { // Thumb Opc S Shift Imm
2660 { // ARM Opc S Shift Imm
2668 { // Thumb Opc S Shift Imm
2695 unsigned Opc = ITP->Opc;
2696 assert(ARM::KILL != Opc && "Invalid table entry");
2699 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2724 unsigned Opcode = isLsl ? LSLOpc : Opc;
2782 unsigned Opc = ARM::MOVsr;
2793 Opc = ARM::MOVsi;
2801 if (Opc == ARM::MOVsr) {
2810 TII.get(Opc), ResultReg)
2813 if (Opc == ARM::MOVsi)
2815 else if (Opc == ARM::MOVsr) {
2900 uint16_t Opc[2]; // ARM, Thumb.
2934 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2973 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), TempReg)
2978 if (Opc == ARM::LDRcp)
2984 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2986 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2987 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)