Lines Matching defs:RegSpc

518 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
521   if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
526   } else if (RegSpc == SingleHighQSpc) {
531   } else if (RegSpc == SingleHighTSpc) {
536   } else if (RegSpc == EvenDblSpc) {
542     assert(RegSpc == OddDblSpc && "unknown register spacing");
559   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
581     if (RegSpc == EvenDblSpc) {
584       assert(RegSpc == OddDblSpc && "Unexpected spacing!");
593     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
643   if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc ||
644       RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc)
677   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
719   GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
753   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
765   assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
766   if (RegSpc == EvenDblSpc && Lane >= RegElts) {
767     RegSpc = OddDblSpc;
778     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
801     GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);