Lines Matching defs:MBBI
64 MachineBasicBlock::iterator MBBI,
67 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
68 void ExpandVST(MachineBasicBlock::iterator &MBBI);
69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
72 void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
74 MachineBasicBlock::iterator &MBBI);
76 MachineBasicBlock::iterator &MBBI);
78 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
82 MachineBasicBlock::iterator MBBI);
84 MachineBasicBlock::iterator MBBI,
87 MachineBasicBlock::iterator MBBI,
90 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
94 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
98 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
101 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
104 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
107 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
110 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
115 MachineBasicBlock::iterator MBBI,
552 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
553 MachineInstr &MI = *MBBI;
562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
670 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
671 MachineInstr &MI = *MBBI;
680 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
746 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
747 MachineInstr &MI = *MBBI;
757 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
836 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
838 MachineInstr &MI = *MBBI;
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
873 void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) {
874 MachineInstr &MI = *MBBI;
881 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
994 MachineBasicBlock::iterator &MBBI) {
995 MachineInstr &MI = *MBBI;
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
1036 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Op), DstReg)
1054 (--MBBI)->getOperand(0).setIsDead(DstIsDead);
1060 MachineBasicBlock::iterator &MBBI) {
1061 MachineInstr &MI = *MBBI;
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg);
1091 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri))
1127 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
1139 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
1153 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
1178 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1185 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL));
1196 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg)
1201 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M))
1243 MachineBasicBlock::iterator MBBI) {
1245 (void)determineFPRegsToClear(*MBBI, ClearRegs);
1248 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1250 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs);
1257 MachineBasicBlock::iterator MBBI,
1262 auto &RetI = *MBBI;
1279 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end());
1366 MachineBasicBlock::iterator MBBI,
1368 auto &RetI = *MBBI;
1381 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1392 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1403 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1406 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
1408 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
1413 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1421 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1429 for (const MachineOperand &Op : MBBI->operands()) {
1442 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1456 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1474 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1497 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1505 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg)
1513 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
1517 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1)
1523 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg)
1532 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg)
1536 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1546 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR))
1551 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator());
1556 MachineBasicBlock::iterator MBBI,
1560 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs);
1567 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1589 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
1596 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1599 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP)
1608 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1611 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
1613 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs);
1617 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1628 for (const MachineOperand &Op : MBBI->operands()) {
1641 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1655 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1673 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD))
1679 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS))
1689 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1732 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1737 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1743 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1763 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1765 if (!definesOrUsesFPReg(*MBBI)) {
1767 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS))
1773 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1780 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1786 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post),
1794 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
1806 MachineBasicBlock::iterator MBBI,
1812 MachineInstr &MI = *MBBI;
1843 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
1938 MachineBasicBlock::iterator MBBI,
1942 MachineInstr &MI = *MBBI;
2044 MachineBasicBlock::iterator MBBI, int JumpReg,
2046 const DebugLoc &DL = MBBI->getDebugLoc();
2049 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2065 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2071 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2083 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2086 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
2092 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
2104 MachineBasicBlock::iterator MBBI, int JumpReg,
2106 const DebugLoc &DL = MBBI->getDebugLoc();
2109 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2112 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R)
2117 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2122 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
2131 MachineBasicBlock::iterator MBBI,
2133 MachineInstr &MI = *MBBI;
2145 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2155 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2166 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2176 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc))
2184 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2202 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
2203 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2204 MBBI--;
2205 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2206 MBBI--;
2207 assert(MBBI->isReturn() &&
2209 unsigned RetOpcode = MBBI->getOpcode();
2210 DebugLoc dl = MBBI->getDebugLoc();
2215 MBBI = MBB.getLastNonDebugInstr();
2216 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2217 MBBI--;
2218 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2219 MBBI--;
2220 MachineOperand &JumpTarget = MBBI->getOperand(0);
2232 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
2250 BuildMI(MBB, MBBI, dl,
2255 auto NewMI = std::prev(MBBI);
2256 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
2257 NewMI->addOperand(MBBI->getOperand(i));
2266 MBB.erase(MBBI);
2268 MBBI = NewMI;
2275 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT));
2277 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI);
2281 BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
2292 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
2297 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2298 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs,
2302 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(),
2312 DebugLoc DL = MBBI->getDebugLoc();
2313 Register JumpReg = MBBI->getOperand(0).getReg();
2321 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse()))
2323 LiveRegs.stepBackward(*MBBI);
2325 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
2329 determineGPRegsToClear(*MBBI,
2342 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg)
2351 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg)
2355 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg)
2362 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
2364 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg);
2367 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr))
2376 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers
2378 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction());
2387 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
2400 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
2441 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2453 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2467 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2490 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2516 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2519 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2522 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2538 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
2552 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2564 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2588 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2596 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2602 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2623 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
2628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
2679 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
2687 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
2717 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg)
2722 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
2728 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2746 ExpandMOV32BitImm(MBB, MBBI);
2750 ExpandTMOV32BitImm(MBB, MBBI);
2761 ExpandTMOV32BitImm(MBB, MBBI);
2765 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
2778 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
2809 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
2968 ExpandVLD(MBBI);
3058 ExpandVST(MBBI);
3133 ExpandLaneOp(MBBI);
3136 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
3137 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
3138 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
3139 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
3145 ExpandMQQPRLoadStore(MBBI);
3150 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3154 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3158 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3162 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3166 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3170 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3173 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
3183 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
3188 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
3191 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
3198 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
3227 BuildMI(MBB, MBBI, MI.getDebugLoc(),
3246 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
3247 while (MBBI != E) {
3248 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
3249 Modified |= ExpandMI(MBB, MBBI, NMBBI);
3250 MBBI = NMBBI;