Lines Matching +full:fiq +full:- +full:based
1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
50 #define DEBUG_TYPE "arm-register-info"
64 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
66 const Function &F = MF->getFunction();
83 // M-class CPUs have hardware which saves the registers needed to allow a
86 } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
87 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
88 // need to be saved to restore user-mode state.
91 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
97 if (STI.getTargetLowering()->supportSwiftError() &&
107 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
124 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
125 MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
143 if (STI.getTargetLowering()->supportSwiftError() &&
204 // FIXME: avoid re-calculating this every time.
210 if (TFI->isFPReserved(MF))
217 // Reserve D16-D31 if the subtarget doesn't support them.
247 if (TFI->isFPReserved(MF))
259 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
261 switch (Super->getID()) {
304 switch (RC->getID()) {
312 ? TFI->hasFP(MF) : true;
313 return 5 - HasFP;
317 ? TFI->hasFP(MF) : true;
318 return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
322 return 32 - 10;
329 for (MCPhysReg Super : RI->superregs(Reg))
331 return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
353 if (MRI.getRegClass(VirtReg)->contains(ARM::LR))
370 } else if (VRM && VRM->hasPhys(Paired)) {
371 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
394 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(Reg);
402 Hint = MRI->getRegAllocationHint(OtherReg);
405 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
407 MRI->setRegAllocationHint(NewReg,
424 if (hasStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
441 if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() &&
448 if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))
464 if (!MRI->canReserveReg(STI.getFramePointerReg()))
468 if (TFI->hasReservedCallFrame(MF))
472 return MRI->canReserveReg(BasePtr);
489 if (TFI->hasFP(MF))
494 /// emitLoadConstPool - Emits a load from constpool to materialize the
505 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
532 const MCInstrDesc &Desc = MI->getDesc();
543 InstrOffs = MI->getOperand(Idx+1).getImm();
548 const MachineOperand &OffOp = MI->getOperand(Idx+1);
551 InstrOffs = -InstrOffs;
557 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
558 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
559 InstrOffs = -InstrOffs;
563 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
564 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
565 InstrOffs = -InstrOffs;
569 InstrOffs = MI->getOperand(ImmIdx).getImm();
579 /// needsFrameBaseReg - Returns true if the instruction's frame index
585 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
586 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
591 // based on the size of the local frame and some conservative assumptions
592 // about the rest of the stack frame (note, this is pre-regalloc, so
598 unsigned Opc = MI->getOpcode();
613 // objects, all fixed-size local references will be via the frame pointer,
615 // Note that the incoming offset is based on the SP value at function entry,
617 MachineFunction &MF = *MI->getParent()->getParent();
623 // Conservatively assume all callee-saved registers get pushed. R4-R6
626 int64_t FPOffset = Offset - 8;
627 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
628 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
629 FPOffset -= 80;
633 // allocation, so adjust our SP-relative offset by that allocation size.
642 // don't know for sure yet whether we'll need that, so we guess based
644 if (TFI->hasFP(MF) &&
645 !((MFI.getLocalFrameMaxAlign() > TFI->getStackAlign()) &&
662 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
668 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
669 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
670 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
672 MachineBasicBlock::iterator Ins = MBB->begin();
674 if (Ins != MBB->end())
675 DL = Ins->getDebugLoc();
677 const MachineFunction &MF = *MBB->getParent();
678 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
687 if (!AFI->isThumb1OnlyFunction())
700 int Off = Offset; // ARM doesn't need the general 64-bit offsets
703 assert(!AFI->isThumb1OnlyFunction() &&
711 if (!AFI->isThumbFunction())
714 assert(AFI->isThumb2Function());
724 const MCInstrDesc &Desc = MI->getDesc();
727 for (; !MI->getOperand(i).isFI(); ++i)
728 assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
743 // based on Offset sign, consider the appropriate instruction
747 Offset = -Offset;
776 if ((Offset & (Scale-1)) != 0)
780 Offset = -Offset;
782 unsigned Mask = (1 << NumBits) - 1;
800 assert(!AFI->isThumb1OnlyFunction() &&
805 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
812 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
813 assert(TFI->hasReservedCallFrame(MF) &&
822 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
826 if (!AFI->isThumbFunction())
829 assert(AFI->isThumb2Function());
850 ARMCC::CondCodes Pred = (PIdx == -1)
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
856 TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
858 if (Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)))
863 if (!AFI->isThumbFunction())
867 assert(AFI->isThumb2Function());
884 auto MBB = MI->getParent();
885 auto MF = MBB->getParent();
886 const MachineRegisterInfo &MRI = MF->getRegInfo();
887 // If not copying into a sub-register this should be ok because we shouldn't
897 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
899 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
901 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
913 auto AFI = MF->getInfo<ARMFunctionInfo>();
914 auto It = AFI->getCoalescedWeight(MBB);
916 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
917 << It->second << "\n");
918 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
923 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
924 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
927 unsigned SizeMultiplier = MBB->size()/100;
929 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
930 It->second += NewRCWeight.RegWeight;