Lines Matching defs:UseIdx

3953                                   unsigned UseIdx, unsigned UseAlign) const {
3954   int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3956     return ItinData->getOperandCycle(UseClass, UseIdx);
3992                                  unsigned UseIdx, unsigned UseAlign) const {
3993   int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3995     return ItinData->getOperandCycle(UseClass, UseIdx);
4020     unsigned UseIdx, unsigned UseAlign) const {
4024   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4025     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4075     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4084     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4102     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4119                                           UseClass, UseIdx))
4122                                                UseClass, UseIdx)) {
4155                                            unsigned &UseIdx, unsigned &Dist) {
4178   UseIdx = Idx;
4365     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4387         getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4394       Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4401     unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4428   if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4440       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4460                                     SDNode *UseNode, unsigned UseIdx) const {
4490       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4809                                              unsigned UseIdx) const {
4818       SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);