Lines Matching defs:Lane
5076 unsigned SReg, unsigned &Lane) {
5078 Lane = 0;
5083 Lane = 1;
5098 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
5099 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
5107 unsigned Lane, unsigned &ImplicitSReg) {
5117 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
5135 unsigned Lane;
5178 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
5180 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
5186 .addImm(Lane)
5202 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
5205 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
5211 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
5217 .addImm(Lane)
5248 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
5275 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)