Lines Matching defs:ItinData

3461 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3466     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3763 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3765   if (!ItinData || ItinData->isEmpty())
3770   int ItinUOps = ItinData->getNumMicroOps(Class);
3773       return getNumMicroOpsSwiftLdSt(ItinData, MI);
3877 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3883     return ItinData->getOperandCycle(DefClass, DefIdx);
3917 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3923     return ItinData->getOperandCycle(DefClass, DefIdx);
3951 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3956     return ItinData->getOperandCycle(UseClass, UseIdx);
3990 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3995     return ItinData->getOperandCycle(UseClass, UseIdx);
4018     const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID,
4025     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4034     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4043     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4064     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4075     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4084     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4102     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4118       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4121     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4364     const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4367   if (!ItinData || ItinData->isEmpty())
4393       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4398     const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4413     unsigned Latency = getInstrLatency(ItinData, DefMI);
4440       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4458 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4469   if (!ItinData || ItinData->isEmpty())
4474         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4490       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4735 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4750         Latency += getInstrLatency(ItinData, *I, PredCost);
4764   if (!ItinData)
4770   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4771     return getNumMicroOps(ItinData, MI);
4774   unsigned Latency = ItinData->getStageLatency(Class);
4786 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4791   if (!ItinData || ItinData->isEmpty())
4797     return ItinData->getStageLatency(get(Opcode).getSchedClass());
4828   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4829   if (!ItinData || ItinData->isEmpty())
4836         ItinData->getOperandCycle(DefClass, DefIdx);