Lines Matching defs:DReg

5077   unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
5080   if (DReg != ARM::NoRegister)
5081    return DReg;
5084   DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
5086   assert(DReg && "S-register with no D super-register?");
5087   return DReg;
5106                                        MachineInstr &MI, unsigned DReg,
5110   if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
5116   ImplicitSReg = TRI->getSubReg(DReg,
5134   unsigned DstReg, SrcReg, DReg;
5178     DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
5185         .addReg(DReg, RegState::Undef)
5202     DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
5205     if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
5214     MIB.addReg(DReg, RegState::Define)
5215         .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5388     unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
5390     if (!DReg || !MI.definesRegister(DReg, TRI))
5409   unsigned DReg = Reg;
5413     DReg = ARM::D0 + (Reg - ARM::S0) / 2;
5414     assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
5417   assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
5418   assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
5428   BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
5431   MI.addRegisterKilled(DReg, TRI, true);