Lines Matching defs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
13 #include "ARMBaseInstrInfo.h"
116 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
130 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
143 ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(
165 ScheduleHazardRecognizer *ARMBaseInstrInfo::
180 ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
356 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
472 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
499 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
551 bool ARMBaseInstrInfo::
561 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
577 std::string ARMBaseInstrInfo::createMIROperandComment(
602 bool ARMBaseInstrInfo::PredicateInstruction(
636 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
662 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
686 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
718 return !ARMBaseInstrInfo::isCPSRDefined(*MI);
725 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
779 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
817 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
828 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
848 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
892 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1059 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
1075 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
1105 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1116 void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1308 Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1360 Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1373 void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1559 Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1617 Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1632 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1635 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1686 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1809 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1837 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
1861 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1948 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2015 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2045 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2095 bool ARMBaseInstrInfo::
2121 bool ARMBaseInstrInfo::
2186 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,
2200 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const {
2223 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
2256 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
2285 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
2319 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
2341 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2473 const ARMBaseInstrInfo &TII,
2633 const ARMBaseInstrInfo &TII) {
2788 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3014 bool ARMBaseInstrInfo::optimizeCompareInstr(
3294 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
3312 bool ARMBaseInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3709 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3763 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3877 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3917 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3951 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3990 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
4017 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
4363 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
4397 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatencyImpl(
4458 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4716 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4735 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4786 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4804 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4825 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4842 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4913 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
5006 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
5042 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
5132 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
5340 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
5401 void ARMBaseInstrInfo::breakPartialRegDependency(
5434 bool ARMBaseInstrInfo::hasNOP() const {
5438 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
5452 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
5479 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
5502 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
5530 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5536 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5548 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
5562 ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const {
5823 ARMBaseInstrInfo::findRegisterToSaveLRTo(outliner::Candidate &C) const {
5875 ARMBaseInstrInfo::getOutliningCandidateInfo(
6094 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,
6197 void ARMBaseInstrInfo::mergeOutliningCandidateAttributes(
6209 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(
6232 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
6281 ARMBaseInstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT,
6426 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {
6432 void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
6493 void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
6508 void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
6569 void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
6582 void ARMBaseInstrInfo::buildOutlinedFrame(
6658 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
6722 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
6727 bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable(
6976 ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {