Lines Matching +full:ats +full:- +full:supported
1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //===----------------------------------------------------------------------===//
51 #define DEBUG_TYPE "asm-printer"
56 MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
64 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
68 if (AFI->isThumbFunction()) {
69 OutStreamer->emitAssemblerFlag(MCAF_Code16);
70 OutStreamer->emitThumbFunc(CurrentFnSym);
72 OutStreamer->emitAssemblerFlag(MCAF_Code32);
75 // Emit symbol for CMSE non-secure entry point
76 if (AFI->isCmseNSEntryFunction()) {
78 OutContext.getOrCreateSymbol("__acle_se_" + CurrentFnSym->getName());
79 emitLinkage(&MF->getFunction(), S);
80 OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
81 OutStreamer->emitLabel(S);
87 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
90 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
95 (Subtarget->isTargetELF()
100 OutStreamer->emitValue(E, Size);
110 /// runOnMachineFunction - This uses the emitInstruction()
125 for (const auto *GV : AFI->getGlobalsPromotedToConstantPool())
150 if (OptimizationGoals == -1) // uninitialized goals
155 if (Subtarget->isTargetCOFF()) {
161 OutStreamer->beginCOFFSymbolDef(CurrentFnSym);
162 OutStreamer->emitCOFFSymbolStorageClass(Scl);
163 OutStreamer->emitCOFFSymbolType(Type);
164 OutStreamer->endCOFFSymbolDef();
177 OutStreamer->emitAssemblerFlag(MCAF_Code16);
180 OutStreamer->emitLabel(TIP.second);
211 GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
217 const MachineOperand &MO = MI->getOperand(OpNum);
226 const MachineFunction &MF = *MI->getParent()->getParent();
228 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
252 MO.getMBB()->getSymbol()->print(O, MAI);
259 if (Subtarget->genExecuteOnly())
260 llvm_unreachable("execute-only should not generate constant pools");
261 GetCPISymbol(MO.getIndex())->print(O, MAI);
275 //===--------------------------------------------------------------------===//
301 if (MI->getOperand(OpNum).isReg()) {
302 MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
303 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
304 // Find the 'd' register that has this 's' register as a sub-register,
306 for (MCPhysReg SR : TRI->superregs(Reg)) {
309 bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg;
316 if (!MI->getOperand(OpNum).isImm())
318 O << ~(MI->getOperand(OpNum).getImm());
321 if (!MI->getOperand(OpNum).isImm())
323 O << (MI->getOperand(OpNum).getImm() & 0xffff);
326 if (!MI->getOperand(OpNum).isReg())
328 const MachineOperand &MO = MI->getOperand(OpNum);
330 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
335 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
338 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
347 while (MI->getOperand(RegOps).isReg()) {
349 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
361 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
371 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
372 unsigned OpFlags = MI->getOperand(OpNum).getImm();
376 F = InlineAsm::Flag(MI->getOperand(OpNum).getImm());
397 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
399 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
402 const MachineOperand &MO = MI->getOperand(OpNum);
405 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
407 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
414 if (RegOp >= MI->getNumOperands())
416 const MachineOperand &MO = MI->getOperand(RegOp);
426 if (!MI->getOperand(OpNum).isReg())
428 Register Reg = MI->getOperand(OpNum).getReg();
431 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
433 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
438 // This modifier is not yet supported.
441 case 'H': { // The highest-numbered register of a pair.
442 const MachineOperand &MO = MI->getOperand(OpNum);
445 const MachineFunction &MF = *MI->getParent()->getParent();
450 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
472 if (!MI->getOperand(OpNum).isReg())
474 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
479 const MachineOperand &MO = MI->getOperand(OpNum);
495 OutStreamer->emitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
502 OutStreamer->emitAssemblerFlag(MCAF_SyntaxUnified);
512 OutStreamer->emitAssemblerFlag(MCAF_Code16);
530 // pointers need to be indirect and pc-rel. We accomplish this by
542 // All darwin targets use mach-o.
546 MMI->getObjFileInfo<MachineModuleInfoMachO>();
548 // Output non-lazy-pointers for external and common global variables.
553 OutStreamer->switchSection(TLOFMacho.getNonLazySymbolPointerSection());
560 OutStreamer->addBlankLine();
566 OutStreamer->switchSection(TLOFMacho.getThreadLocalPointerSection());
573 OutStreamer->addBlankLine();
581 OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
585 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
586 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
589 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
590 Subtarget->isTargetMuslAEABI()))
591 ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
592 OptimizationGoals = -1;
594 ATS.finishAttributeSection();
597 //===----------------------------------------------------------------------===//
600 // The following seem like one-off assembler flags, but they actually need
624 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
625 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
627 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
629 ATS.switchVendor("aeabi");
652 ATS.emitTargetAttributes(STI);
656 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
660 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
666 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
672 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
675 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
680 if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
682 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
684 else if (checkDenormalAttributeConsistency(*MMI->getModule(),
685 "denormal-fp-math",
687 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
690 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
701 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
707 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
719 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
720 "no-trapping-math", "true") ||
722 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
725 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
728 // rounding at run-time, emit the rounding attribute.
730 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
734 // equivalent of GCC's -ffinite-math-only flag.
736 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
739 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
743 // 8-bytes alignment stuff.
744 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
745 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
747 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
749 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
752 // -mfp16-format option and associated plumbing must be
753 // supported. For now the __fp16 type is exposed by default, so this
755 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
758 if (const Module *SourceModule = MMI->getModule()) {
762 SourceModule->getModuleFlag("wchar_size"))) {
763 int WCharWidth = WCharWidthValue->getZExtValue();
766 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
773 SourceModule->getModuleFlag("min_enum_size"))) {
774 int EnumWidth = EnumWidthValue->getZExtValue();
778 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
782 SourceModule->getModuleFlag("sign-return-address"));
783 if (PACValue && PACValue->isOne()) {
788 ATS.emitAttribute(ARMBuildAttrs::PAC_extension,
791 ATS.emitAttribute(ARMBuildAttrs::PACRET_use, ARMBuildAttrs::PACRETUsed);
795 SourceModule->getModuleFlag("branch-target-enforcement"));
796 if (BTIValue && BTIValue->isOne()) {
801 ATS.emitAttribute(ARMBuildAttrs::BTI_extension,
804 ATS.emitAttribute(ARMBuildAttrs::BTI_use, ARMBuildAttrs::BTIUsed);
810 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
813 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
816 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
820 //===----------------------------------------------------------------------===//
861 if (Subtarget->isTargetMachO()) {
863 (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
871 MMI->getObjFileInfo<MachineModuleInfoMachO>();
873 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
878 !GV->hasInternalLinkage());
880 } else if (Subtarget->isTargetCOFF()) {
881 assert(Subtarget->isTargetWindows() &&
882 "Windows is the only supported COFF target");
900 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
909 } else if (Subtarget->isTargetELF()) {
918 int Size = DL.getTypeAllocSize(MCPV->getType());
922 if (ACPV->isPromotedGlobal()) {
933 for (const auto *GV : ACPC->promotedGlobals()) {
936 OutStreamer->emitLabel(GVSym);
940 return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
944 if (ACPV->isLSDA()) {
945 MCSym = getMBBExceptionSym(MF->front());
946 } else if (ACPV->isBlockAddress()) {
948 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
950 } else if (ACPV->isGlobalValue()) {
951 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
953 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
955 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
957 } else if (ACPV->isMachineBasicBlock()) {
958 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
959 MCSym = MBB->getSymbol();
961 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
962 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
968 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
971 if (ACPV->getPCAdjustment()) {
974 ACPV->getLabelId(), OutContext);
978 MCConstantExpr::create(ACPV->getPCAdjustment(),
981 if (ACPV->mustAddCurrentAddress()) {
982 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
985 OutStreamer->emitLabel(DotSym);
991 OutStreamer->emitValue(Expr, Size);
995 const MachineOperand &MO1 = MI->getOperand(1);
998 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1004 OutStreamer->emitLabel(JTISymbol);
1006 // Mark the jump table as data-in-code.
1007 OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
1010 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1011 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1016 // (BasicBlockAddr - TableBeginAddr)
1021 // .word (LBB0 - LJTI_0_0)
1022 // .word (LBB1 - LJTI_0_0)
1023 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
1025 if (isPositionIndependent() || Subtarget->isROPI())
1031 else if (AFI->isThumbFunction())
1034 OutStreamer->emitValue(Expr, 4);
1036 // Mark the end of jump table data-in-code region.
1037 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1041 const MachineOperand &MO1 = MI->getOperand(1);
1044 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1050 OutStreamer->emitLabel(JTISymbol);
1053 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1054 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1058 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1071 const MachineOperand &MO1 = MI->getOperand(1);
1074 if (Subtarget->isThumb1Only())
1078 OutStreamer->emitLabel(JTISymbol);
1081 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1082 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1085 // Mark the jump table as data-in-code.
1086 OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1090 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1094 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1099 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1100 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1103 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1110 OutStreamer->emitValue(Expr, OffsetWidth);
1112 // Mark the end of jump table data-in-code region. 32-bit offsets use
1113 // actual branch instructions here, so we don't mark those as a data-region
1115 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1117 // Make sure the next instruction is 2-byte aligned.
1129 switch (BranchInstr->getOpcode()) {
1139 // half-word shifted left, relative to *after* the branch instruction.
1141 BranchLabel = GetCPISymbol(BranchInstr->getOperand(3).getImm());
1149 BranchLabel = GetCPISymbol(BranchInstr->getOperand(3).getImm());
1166 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1169 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1170 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1171 const MachineFunction &MF = *MI->getParent()->getParent();
1176 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1177 unsigned Opc = MI->getOpcode();
1203 // So we need to special-case MOVS, ADDS and LSLS, and keep track of
1208 DstReg = MI->getOperand(0).getReg();
1211 SrcReg = MI->getOperand(1).getReg();
1212 DstReg = MI->getOperand(0).getReg();
1217 if (MI->mayStore()) {
1220 "Only stack pointer as a destination reg is supported");
1236 MI->print(errs());
1246 "Only stack pointer as a source reg is supported");
1247 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1249 const MachineOperand &MO = MI->getOperand(i);
1262 TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1269 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1277 assert(MI->getOperand(2).getReg() == ARM::SP &&
1278 "Only stack pointer as a source reg is supported");
1279 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1285 assert(MI->getOperand(3).getReg() == ARM::SP &&
1286 "Only stack pointer as a source reg is supported");
1287 SrcReg = MI->getOperand(1).getReg();
1288 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1291 SrcReg = MI->getOperand(2).getReg();
1292 if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1295 PadBefore = -MI->getOperand(4).getImm() - 8;
1298 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1300 ATS.emitPad(PadBefore);
1301 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1304 ATS.emitPad(PadAfter);
1312 MI->print(errs());
1323 Offset = -MI->getOperand(2).getImm();
1330 Offset = MI->getOperand(2).getImm();
1333 Offset = MI->getOperand(2).getImm()*4;
1337 Offset = -MI->getOperand(2).getImm()*4;
1341 -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1345 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1347 // Set-up of the frame pointer. Positive values correspond to "add"
1349 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1353 ATS.emitPad(Offset);
1357 ATS.emitMovSP(DstReg, -Offset);
1361 MI->print(errs());
1367 // If a Thumb1 function spills r8-r11, we copy the values to low
1370 AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1375 unsigned CPI = MI->getOperand(1).getIndex();
1377 if (CPI >= MCP->getConstants().size())
1378 CPI = AFI->getOriginalCPIdx(CPI);
1379 assert(CPI != -1U && "Invalid constpool index");
1382 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1384 Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1385 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1389 Offset = MI->getOperand(1).getImm();
1390 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1393 Offset = MI->getOperand(2).getImm();
1394 AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1397 Offset = MI->getOperand(2).getImm();
1398 AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1401 assert(MI->getOperand(3).getImm() == 8 &&
1403 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1405 AFI->EHPrologueOffsetInRegs[DstReg] <<= 8;
1408 assert(MI->getOperand(2).getReg() == MI->getOperand(0).getReg() &&
1410 Offset = MI->getOperand(3).getImm();
1411 AFI->EHPrologueOffsetInRegs[DstReg] += Offset;
1415 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1418 MI->print(errs());
1425 // Simple pseudo-instructions have their lowering (with expansion to real
1426 // instructions) auto-generated.
1431 // ARM_MC::verifyInstructionPredicates(MI->getOpcode(),
1435 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1436 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1439 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1440 OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1444 // Emit unwinding stuff for frame-related instructions
1445 if (Subtarget->isTargetEHABICompatible() &&
1446 MI->getFlag(MachineInstr::FrameSetup))
1449 // Do any auto-generated pseudo lowerings.
1453 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1457 unsigned Opc = MI->getOpcode();
1465 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1466 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1468 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1470 .addReg(MI->getOperand(0).getReg())
1473 .addImm(MI->getOperand(2).getImm())
1474 .addReg(MI->getOperand(3).getReg()));
1481 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1482 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1484 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1486 .addReg(MI->getOperand(0).getReg())
1489 .addImm(MI->getOperand(2).getImm())
1490 .addReg(MI->getOperand(3).getReg()));
1505 assert(Subtarget->hasV4TOps());
1507 .addReg(MI->getOperand(0).getReg()));
1511 if (Subtarget->hasV5TOps())
1520 Register TReg = MI->getOperand(0).getReg();
1534 // Create a link-saving branch to the Reg Indirect Jump Pad.
1553 .addReg(MI->getOperand(0).getReg())
1571 const MachineOperand &Op = MI->getOperand(0);
1587 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1589 unsigned TF = MI->getOperand(1).getTargetFlags();
1590 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1596 MI->getOperand(2).getImm(), OutContext);
1619 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1620 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1622 unsigned TF = MI->getOperand(2).getTargetFlags();
1623 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1629 MI->getOperand(3).getImm(), OutContext);
1655 MI->getOperand(0).getIndex(), OutContext),
1659 if (MI->getOperand(1).isReg()) {
1661 MCInst.addReg(MI->getOperand(1).getReg());
1665 if (MI->getOperand(1).isMBB())
1667 MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1668 else if (MI->getOperand(1).isGlobal()) {
1669 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1671 GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1672 } else if (MI->getOperand(1).isSymbol()) {
1674 GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1685 MI->getOperand(2).getIndex(), OutContext),
1688 MCInst.addImm(MI->getOperand(3).getImm());
1690 MCInst.addImm(MI->getOperand(2).getImm())
1691 .addReg(MI->getOperand(3).getReg());
1701 OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1703 MI->getOperand(0).getIndex(), OutContext));
1713 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1715 MI->getOperand(2).getImm(), OutContext));
1719 .addReg(MI->getOperand(0).getReg())
1720 .addReg(MI->getOperand(0).getReg())
1734 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1736 MI->getOperand(2).getImm(), OutContext));
1740 .addReg(MI->getOperand(0).getReg())
1742 .addReg(MI->getOperand(1).getReg())
1744 .addImm(MI->getOperand(3).getImm())
1745 .addReg(MI->getOperand(4).getReg())
1762 // a PC-relative address at the ldr instruction.
1765 OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1767 MI->getOperand(2).getImm(), OutContext));
1771 switch (MI->getOpcode()) {
1784 .addReg(MI->getOperand(0).getReg())
1786 .addReg(MI->getOperand(1).getReg())
1789 .addImm(MI->getOperand(3).getImm())
1790 .addReg(MI->getOperand(4).getReg()));
1795 if (Subtarget->genExecuteOnly())
1796 llvm_unreachable("execute-only should not generate constant pools");
1798 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1803 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1804 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1808 OutStreamer->emitDataRegion(MCDR_DataRegion);
1812 OutStreamer->emitLabel(GetCPISymbol(LabelId));
1814 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1829 emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1834 .addReg(MI->getOperand(0).getReg())
1842 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1844 OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1846 .addReg(MI->getOperand(0).getReg())
1847 .addReg(MI->getOperand(1).getReg())
1856 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1857 Register Base = MI->getOperand(0).getReg();
1858 Register Idx = MI->getOperand(1).getReg();
1859 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1881 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1885 // for load indexes which are currently not supported.
1886 OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
1928 OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1942 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1946 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1961 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1962 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1974 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1975 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1976 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1987 .addReg(MI->getOperand(0).getReg())
1988 .addReg(MI->getOperand(1).getReg())
1997 OutStreamer->emitZeros(MI->getOperand(1).getImm());
2000 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2002 if (!Subtarget->isTargetMachO()) {
2004 OutStreamer->AddComment("trap");
2005 ATS.emitInst(Val);
2012 OutStreamer->AddComment("trap");
2013 ATS.emitInst(Val);
2017 // Non-Darwin binutils don't yet support the "trap" mnemonic.
2019 if (!Subtarget->isTargetMachO()) {
2021 OutStreamer->AddComment("trap");
2022 ATS.emitInst(Val, 'n');
2038 Register SrcReg = MI->getOperand(0).getReg();
2039 Register ValReg = MI->getOperand(1).getReg();
2041 OutStreamer->AddComment("eh_setjmp begin");
2083 OutStreamer->AddComment("eh_setjmp end");
2092 OutStreamer->emitLabel(Label);
2104 Register SrcReg = MI->getOperand(0).getReg();
2105 Register ValReg = MI->getOperand(1).getReg();
2107 OutStreamer->AddComment("eh_setjmp begin");
2145 OutStreamer->AddComment("eh_setjmp end");
2161 Register SrcReg = MI->getOperand(0).getReg();
2162 Register ScratchReg = MI->getOperand(1).getReg();
2179 const MachineFunction &MF = *MI->getParent()->getParent();
2210 assert(Subtarget->hasV4TOps());
2224 Register SrcReg = MI->getOperand(0).getReg();
2225 Register ScratchReg = MI->getOperand(1).getReg();
2227 const MachineFunction &MF = *MI->getParent()->getParent();
2295 Register SrcReg = MI->getOperand(0).getReg();
2373 ATS.emitARMWinCFIAllocStack(MI->getOperand(0).getImm(),
2374 MI->getOperand(1).getImm());
2379 ATS.emitARMWinCFISaveRegMask(MI->getOperand(0).getImm(),
2380 MI->getOperand(1).getImm());
2384 ATS.emitARMWinCFISaveSP(MI->getOperand(0).getImm());
2388 ATS.emitARMWinCFISaveFRegs(MI->getOperand(0).getImm(),
2389 MI->getOperand(1).getImm());
2393 ATS.emitARMWinCFISaveLR(MI->getOperand(0).getImm());
2398 ATS.emitARMWinCFINop(MI->getOperand(0).getImm());
2402 ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2406 ATS.emitARMWinCFIEpilogStart(ARMCC::AL);
2410 ATS.emitARMWinCFIEpilogEnd();
2426 //===----------------------------------------------------------------------===//
2428 //===----------------------------------------------------------------------===//