Lines Matching defs:Out
417 Register Out =
420 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
425 return Out;
433 Register Out = MRI->createVirtualRegister(TRC);
437 TII->get(TargetOpcode::COPY), Out)
440 return Out;
447 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
451 TII->get(TargetOpcode::REG_SEQUENCE), Out)
456 return Out;
465 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
466 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
471 return Out;
477 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
481 TII->get(TargetOpcode::INSERT_SUBREG), Out)
486 return Out;
493 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
497 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
498 return Out;
510 unsigned Out;
523 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
529 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
534 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
552 Out = createImplicitDef(MBB, InsertPt, DL);
553 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
554 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
557 return Out;