Lines Matching defs:Ldst
75 // Tries to combine \p Ldst with increment of its base register to form
77 MachineInstr *tryToCombine(MachineInstr &Ldst);
79 // Returns true if result of \p Add is not used before \p Ldst
81 const MachineInstr *Ldst);
83 // Returns true if load/store instruction \p Ldst can be hoisted up to
85 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
87 // // Returns true if load/store instruction \p Ldst can be sunk down
89 // bool canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
91 // Check if instructions \p Ldst and \p Add can be moved to become adjacent
93 // If \p Uses is not null, fill it with instructions after \p Ldst which use
94 // \p Ldst's base register
95 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
108 // Change instruction \p Ldst to postincrement form.
111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
193 const MachineInstr *Ldst) {
195 return dominatesAllUsesOf(Ldst, R, MDT, MRI);
198 MachineInstr *ARCOptAddrMode::tryToCombine(MachineInstr &Ldst) {
199 assert(Ldst.mayLoadOrStore() && "LD/ST instruction expected");
203 LLVM_DEBUG(dbgs() << "[ABAW] tryToCombine " << Ldst);
204 if (!AII->getBaseAndOffsetPosition(Ldst, BasePos, OffsetPos)) {
209 MachineOperand &Base = Ldst.getOperand(BasePos);
210 MachineOperand &Offset = Ldst.getOperand(OffsetPos);
238 MachineInstr *MoveTo = canJoinInstructions(&Ldst, &Add, &Uses);
246 LLVM_DEBUG(MachineInstr *First = &Ldst; MachineInstr *Last = &Add;
253 MachineInstr *Result = Ldst.getNextNode();
255 Ldst.removeFromParent();
256 Add.getParent()->insertAfter(Add.getIterator(), &Ldst);
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode());
266 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2));
275 ARCOptAddrMode::canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
277 assert(Ldst && Add && "NULL instruction passed");
280 MachineInstr *Last = Ldst;
281 if (MDT->dominates(Ldst, Add))
283 else if (!MDT->dominates(Add, Ldst))
290 if (!AII->getBaseAndOffsetPosition(*Ldst, BasePos, OffPos)) {
297 Register BaseReg = Ldst->getOperand(BasePos).getReg();
305 if (Ldst->mayStore() && Ldst->getOperand(0).isReg()) {
306 Register StReg = Ldst->getOperand(0).getReg();
316 if (&MI == Ldst || &MI == Add)
318 if (&MI != Add && MDT->dominates(Ldst, &MI))
320 else if (!MDT->dominates(&MI, Ldst))
335 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can sink Add down to Ldst\n");
336 } else if (canHoistLoadStoreTo(Ldst, Add)) {
338 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Ldst to Add\n");
345 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Add to Ldst\n");
348 *Uses = (Result == Ldst) ? UsesAfterLdst : UsesAfterAdd;
399 bool ARCOptAddrMode::canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To) {
400 if (Ldst->getParent() != To->getParent())
402 MachineBasicBlock::const_iterator MI(To), ME(Ldst),
403 End(Ldst->getParent()->end());
405 bool IsStore = Ldst->mayStore();
416 for (auto &O : Ldst->explicit_operands()) {
426 // bool ARCOptAddrMode::canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To) {
428 // if (Ldst->getParent() != To->getParent())
430 // MachineBasicBlock::const_iterator MI(Ldst), ME(To),
431 // End(Ldst->getParent()->end());
433 // bool IsStore = Ldst->mayStore();
434 // bool IsLoad = Ldst->mayLoad();
436 // Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
451 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
454 bool IsStore = Ldst.mayStore();
457 AII->getBaseAndOffsetPosition(Ldst, BasePos, OffPos);
459 Register BaseReg = Ldst.getOperand(BasePos).getReg();
461 Ldst.removeOperand(OffPos);
462 Ldst.removeOperand(BasePos);
465 Src = Ldst.getOperand(BasePos - 1);
466 Ldst.removeOperand(BasePos - 1);
469 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));
472 Ldst.addOperand(Src);
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
474 Ldst.addOperand(NewOffset);
475 LLVM_DEBUG(dbgs() << "[ABAW] New Ldst: " << Ldst);