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1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
65 bit Value = mode;
76 class CacheMode<bit mode, string instSfx, string asmSfx> {
77 bit Value = mode;
116 let TSFlags{1-0} = AA.Value;
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 // All 32-bit ARC instructions have a 5-bit "major" opcode class designator
130 // in bits 27-31.
133 // N - Delay Slot bit. ARC v2 branch instructions have an optional delay slot
134 // which is encoded with this bit. When set, a delay slot exists.
135 // cc - Condition code.
136 // SX - Signed X-bit immediate.
137 // UX - Unsigned X-bit immediate.
139 // [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
142 // a 32-bit Long Immediate (LImm), using 0x3e==62 as the field value.
143 // This makes 32-bit format instructions with Long Immediates
144 // 64-bit instructions, with the Long Immediate in bits 32-63.
145 // A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
149 // or a 6-bit unsigned immediate (immU6), depending on the format.
150 // F - Many instructions specify a flag bit. When set, the result of these
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
158 bit N;
160 let Inst{31-27} = major;
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
168 bits<21> S21; // 2-byte aligned 21-bit byte-offset.
170 let Inst{26-18} = S21{10-2};
171 let Inst{15-6} = S21{20-11};
172 let Inst{4-0} = cc;
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
178 bits<25> S25; // 2-byte aligned 25-bit byte-offset.
179 let Inst{26-18} = S25{10-2};
180 let Inst{15-6} = S25{20-11};
182 let Inst{3-0} = S25{24-21};
190 // Branch targets are 2-byte aligned, so S25[0] is implied 0.
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
192 // |S25[10-1] | 1|S25[20-11] |N|0|S25[24-21]|
198 // BL targets (functions) are 4-byte aligned, so S25[1-0] = 0b00
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
200 // |S25[10-2] | 1| 0|S25[20-11] |N|0|S25[24-21]|
206 // BLcc targets have 21 bit range, and are 4-byte aligned.
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
208 // |S25[10-2] | 0| 0|S25[20-11] |N|0|cc |
214 // BRcc targets have limited 9-bit range. These are for compare and branch
215 // in single instruction. Their targets are 2-byte aligned. They also use
216 // a different (3-bit) set of condition codes.
217 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
218 // |B[2-0] |S9[7-1] | 1|S9[8]|B[5-3] |C |N|u|0|cc |
219 class F32_BR1_BCC<dag outs, dag ins, string asmstr, bit IsU6,
226 bit N;
227 bits<9> S9; // 2-byte aligned 9-bit byte-offset.
229 let Inst{31-27} = 0b00001;
230 let Inst{26-24} = B{2-0};
231 let Inst{23-17} = S9{7-1};
234 let Inst{14-12} = B{5-3};
235 let Inst{11-6} = C;
239 let Inst{2-0} = cc;
243 // Single Operand Instructions. Inst[5-0] specifies the specific operation
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
246 // |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
247 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
254 let Inst{31-27} = major;
255 let Inst{26-24} = B{2-0};
256 let Inst{23-22} = 0b00;
257 let Inst{21-16} = 0b101111;
259 let Inst{14-12} = B{5-3};
260 let Inst{11-6} = C;
261 let Inst{5-0} = subop;
264 // Dual Operand Instructions. Inst[21-16] specifies the specific operation
267 // 3-register Dual Operand instruction.
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
269 // |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
270 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
277 let Inst{31-27} = major;
278 let Inst{26-24} = B{2-0};
279 let Inst{23-22} = 0b00;
280 let Inst{21-16} = subop;
282 let Inst{14-12} = B{5-3};
283 let Inst{11-6} = C;
284 let Inst{5-0} = A;
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
290 // |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
291 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
298 let Inst{31-27} = major;
299 let Inst{26-24} = B{2-0};
300 let Inst{23-22} = 0b11;
301 let Inst{21-16} = subop;
303 let Inst{14-12} = B{5-3};
304 let Inst{11-6} = C;
306 let Inst{4-0} = cc;
310 // 2-register, unsigned 6-bit immediate Dual Operand instruction.
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
312 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
313 class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
320 let Inst{31-27} = major;
321 let Inst{26-24} = B{2-0};
322 let Inst{23-22} = 0b01;
323 let Inst{21-16} = subop;
325 let Inst{14-12} = B{5-3};
326 let Inst{11-6} = U6;
327 let Inst{5-0} = A;
330 // 1-register, unsigned 6-bit, immediate Dual Operand instruction with
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
333 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
334 class F32_DOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
342 let Inst{31-27} = major;
343 let Inst{26-24} = B{2-0};
344 let Inst{23-22} = 0b11;
345 let Inst{21-16} = subop;
347 let Inst{14-12} = B{5-3};
348 let Inst{11-6} = U6;
350 let Inst{4-0} = cc;
355 // 2-register, unsigned 6-bit immediate Dual Operand instruction with
358 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
359 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
360 class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
367 let Inst{31-27} = major;
368 let Inst{26-24} = B{2-0};
369 let Inst{23-22} = 0b11;
370 let Inst{21-16} = subop;
372 let Inst{14-12} = B{5-3};
373 let Inst{11-6} = U6;
375 let Inst{4-0} = cc;
378 // 2-register, signed 12-bit immediate Dual Operand instruction.
379 // This instruction uses B as the first 2 operands (i.e., add B, B, -128).
380 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
381 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
382 class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
388 let Inst{31-27} = major;
389 let Inst{26-24} = B{2-0};
390 let Inst{23-22} = 0b10;
391 let Inst{21-16} = subop;
393 let Inst{14-12} = B{5-3};
394 let Inst{11-6} = S12{5-0};
395 let Inst{5-0} = S12{11-6};
398 // 1-register, signed 12-bit immediate Dual Operand instruction.
400 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
401 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
402 class F32_SOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
408 let Inst{31-27} = major;
409 let Inst{26-24} = B{2-0};
410 let Inst{23-22} = 0b10;
411 let Inst{21-16} = subop;
413 let Inst{14-12} = B{5-3};
414 let Inst{11-6} = S12{5-0};
415 let Inst{5-0} = S12{11-6};
420 // 1-register, unsigned 6-bit immediate Dual Operand instruction.
422 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
423 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |0|0|0|0|0|0|
424 class F32_SOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
430 let Inst{31-27} = major;
431 let Inst{26-24} = B{2-0};
432 let Inst{23-22} = 0b01;
433 let Inst{21-16} = subop;
435 let Inst{14-12} = B{5-3};
436 let Inst{11-6} = U6;
437 let Inst{5-0} = 0;
442 // 2-register, 32-bit immediate (LImm) Dual Operand instruction.
443 // This instruction has the 32-bit immediate in bits 32-63, and
445 class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
452 let Inst{63-32} = LImm;
453 let Inst{31-27} = major;
454 let Inst{26-24} = B{2-0};
455 let Inst{23-22} = 0b00;
456 let Inst{21-16} = subop;
458 let Inst{14-12} = B{5-3};
459 let Inst{11-6} = 0b111110;
460 let Inst{5-0} = A;
467 // di - Uncached bit. When set, loads/stores bypass the cache and access
469 // aa - Incrementing mode. Loads and stores can write-back address pre- or
470 // post- memory operation.
471 // zz - Memory size (can be 8/16/32 bit load/store).
472 // x - Sign-extending. When set, short loads can be sign-extended to 32-bits.
474 // Base Register + Signed 9-bit Immediate: Both Load/Store.
475 // LImm: Both Load/Store (Load/Store from a fixed 32-bit address).
480 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
481 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |di|aa |zz |x|A |
482 class F32_LD_RS9<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
489 let Inst{31-27} = 0b00010;
490 let Inst{26-24} = B{2-0};
491 let Inst{23-16} = S9{7-0};
493 let Inst{14-12} = B{5-3};
495 let Inst{10-9} = aa;
496 let Inst{8-7} = zz;
498 let Inst{5-0} = A;
503 class F32_LD_ADDR<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
508 let B = addr{14-9};
509 let S9 = addr{8-0};
515 // LImm Load. The 32-bit immediate address is in Inst[63-32].
516 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
518 class F32_LD_LIMM<bit x, bit di, bits<2> zz, dag outs, dag ins,
525 let Inst{63-32} = LImm;
526 let Inst{31-27} = 0b00010;
527 let Inst{26-24} = LImmReg{2-0};
528 let Inst{23-15} = 0;
529 let Inst{14-12} = LImmReg{5-3};
531 let Inst{10-9} = 0;
532 let Inst{8-7} = zz;
534 let Inst{5-0} = A;
540 // Register + LImm load. The 32-bit immediate address is in Inst[63-32].
541 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
542 // |B[2-0] |aa | 1| 1| 0|zz | x|di|B[5-3] | 1| 1|1|1|1|0|A |
543 class F32_LD_RLIMM<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
551 let B = addr{37-32};
552 let LImm = addr{31-0};
554 let Inst{63-32} = LImm;
555 let Inst{31-27} = 0b00100;
556 let Inst{26-24} = B{2-0};
557 let Inst{23-22} = aa;
558 let Inst{21-19} = 0b110;
559 let Inst{18-17} = zz;
562 let Inst{14-12} = B{5-3};
563 let Inst{11-6} = LImmReg;
564 let Inst{5-0} = A;
571 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
572 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |C |di|aa |zz |0|
573 class F32_ST_RS9<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
580 let Inst{31-27} = 0b00011;
581 let Inst{26-24} = B{2-0};
582 let Inst{23-16} = S9{7-0};
584 let Inst{14-12} = B{5-3};
585 let Inst{11-6} = C;
587 let Inst{4-3} = aa;
588 let Inst{2-1} = zz;
594 class F32_ST_ADDR<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
599 let B = addr{14-9};
600 let S9 = addr{8-0};
606 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
608 class F32_ST_LIMM<bit di, bits<2> zz, dag outs, dag ins,
615 let Inst{63-32} = LImm;
616 let Inst{31-27} = 0b00011;
617 let Inst{26-24} = LImmReg{2-0};
618 let Inst{23-15} = 0;
619 let Inst{14-12} = LImmReg{5-3};
620 let Inst{11-6} = C;
622 let Inst{4-3} = 0;
623 let Inst{2-1} = zz;
639 let Inst{15-11} = 0b01000;
640 let Inst{7-5} = h{2-0};
642 let Inst{1-0} = h{4-3};
650 let Inst{15-11} = 0b01001;
651 let Inst{10-8} = b;
654 class F16_LD_SUB<bit i, string asmstr> :
661 let Inst{7-5} = c;
664 let Inst{2-0} = a;
671 bit r;
675 let Inst{6-4} = u6{5-3};
677 let Inst{2-0} = u6{2-0};
684 let Inst{15-11} = 0b01010;
687 class F16_LD_ST_s11<bit i, string asmstr> :
692 let Inst{10-5} = s11{10-5};
695 let Inst{2-0} = s11{4-2};
696 let s11{1-0} = 0b00;
706 let Inst{10-8} = b;
707 let Inst{7-4} = u7{6-3};
709 let Inst{2-0} = u7{2-0};
713 class F16_JLI_EI<bit i, string asmstr> :
719 let Inst{15-11} = 0b01011;
721 let Inst{9-0} = u10;
724 // Load/Add Register-Register.
733 let Inst{15-11} = 0b01100;
734 let Inst{10-8} = b;
735 let Inst{7-5} = c;
736 let Inst{4-3} = i;
737 let Inst{2-0} = a;
740 // Load/Add GP-Relative.
744 let Inst{15-11} = 0b11001;
745 let Inst{10-9} = i;
748 // Add/Sub/Shift Register-Immediate.
759 let Inst{15-11} = 0b01101;
760 let Inst{10-8} = b;
761 let Inst{7-5} = c;
762 let Inst{4-3} = i;
763 let Inst{2-0} = u3;
775 let Inst{15-11} = 0b01110;
776 let Inst{10-8} = b_s3;
777 let Inst{7-5} = h{2-0};
778 let Inst{4-2} = i;
779 let Inst{1-0} = h{4-3};
786 let Inst{7-5} = LImmReg{2-0};
787 let Inst{1-0} = LImmReg{4-3};
794 let Inst{47-16} = LImm;
804 let Inst{15-11} = 0b01111;
805 let Inst{10-8} = b;
806 let Inst{7-5} = c;
807 let Inst{4-0} = i;
843 let Inst{15-11} = opc;
844 let Inst{10-8} = b;
845 let Inst{7-5} = c;
852 let Inst{4-0} = off{6-2};
853 let off{1-0} = 0b00;
860 let Inst{4-0} = off{5-1};
868 let Inst{4-0} = off;
871 // Shift/Subtract/Bit Immediate.
880 let Inst{15-11} = 0b10111;
881 let Inst{10-8} = b;
882 let Inst{7-5} = i;
883 let Inst{4-0} = u5;
889 // 16-bit stack-based operations.
899 let Inst{15-11} = 0b11000;
900 let Inst{10-8} = fieldB;
901 let Inst{7-5} = i;
902 let Inst{4-0} = fieldU;
913 let fieldU = u7{6-2};
914 let u7{1-0} = 0b00;
954 let Inst{15-11} = opc;
955 let Inst{10-8} = b;
958 class F16_OP_U7<bit i, string asmstr> :
963 let Inst{6-0} = u7;
1001 class F16_BCC_REG<bit i, string asmstr> :
1008 let Inst{15-11} = 0b11101;
1009 let Inst{10-8} = b;
1011 let Inst{6-0} = s8{7-1};
1019 let Inst{15-11} = 0b11110;
1020 let Inst{10-9} = i;
1028 let Inst{8-0} = s{9-1};
1037 let Inst{8-6} = i;
1038 let Inst{5-0} = s{6-1};