Lines Matching +full:ext +full:- +full:gen
1 //===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
19 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21 let Inst{30-25} = op;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
32 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34 let Inst{30-25} = op;
36 let Inst{63-32} = imm;
43 let Inst{8-0} = 0xf9; // sdwa
44 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46 let Inst{30-25} = op;
54 let Inst{8-0} = 0xf9; // sdwa
55 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57 let Inst{30-25} = op;
112 class VOP2_Real_Gen <VOP2_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
113 VOP2_Real <ps, Gen.Subtarget, real_name> {
114 let AssemblerPredicate = Gen.AssemblerPredicate;
116 let DecoderNamespace = Gen.DecoderNamespace#
214 // any subtarget is a problem. It makes getMCOpcodeGen return -1, which we
303 if !eq(VOPDOp, -1) then
335 : VOP2eInst_Base<opName, P, -1, "", node, revOp, useSGPRInput>;
583 // Suppress src2 implied by type since the 32-bit encoding uses an
624 // Suppress src2 implied by type since the 32-bit encoding uses an
712 //===----------------------------------------------------------------------===//
714 //===----------------------------------------------------------------------===//
901 //===----------------------------------------------------------------------===//
902 // 16-Bit Operand Instructions
903 //===----------------------------------------------------------------------===//
1142 // Note: 16-bit instructions produce a 0 result in the high 16-bits
1159 class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
1160 (i16 (ext i1:$src)),
1185 // Undo sub x, c -> add x, -c canonicalization since c is more likely
1186 // an inline immediate than -c.
1187 // TODO: Also do for 64-bit.
1219 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
1232 let AddedComplexity = 1 in { // Prefer over form with carry-out.
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1272 let Inst{8-0} = 0xfa;
1273 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
1274 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
1275 let Inst{30-25} = op;
1292 class VOP2_DPP16_Gen<bits<6> op, VOP2_DPP_Pseudo ps, GFXGen Gen,
1294 VOP2_DPP16<op, ps, Gen.Subtarget, opName, p> {
1295 let AssemblerPredicate = Gen.AssemblerPredicate;
1297 let DecoderNamespace = Gen.DecoderNamespace#
1312 let Inst{8-0} = fi;
1313 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
1314 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
1315 let Inst{30-25} = op;
1322 class VOP2_DPP8_Gen<bits<6> op, VOP2_Pseudo ps, GFXGen Gen,
1325 let AssemblerPredicate = Gen.AssemblerPredicate;
1327 let DecoderNamespace = Gen.DecoderNamespace#
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 //===------------------------------- VOP2 -------------------------------===//
1336 multiclass VOP2Only_Real_MADK<GFXGen Gen, bits<6> op> {
1337 def Gen.Suffix :
1338 VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME), Gen>,
1339 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1342 multiclass VOP2Only_Real_MADK_with_name<GFXGen Gen, bits<6> op, string asmName,
1344 def Gen.Suffix :
1345 VOP2_Real_Gen<!cast<VOP2_Pseudo>(opName), Gen>,
1346 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
1352 multiclass VOP2_Real_e32<GFXGen Gen, bits<6> op> {
1353 def _e32#Gen.Suffix :
1354 VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME#"_e32"), Gen>,
1355 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1358 multiclass VOP2Only_Real_e32<GFXGen Gen, bits<6> op> {
1360 defm NAME: VOP2_Real_e32<Gen, op>;
1363 multiclass VOP2_Real_e64<GFXGen Gen, bits<6> op> {
1364 def _e64#Gen.Suffix :
1365 VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,
1366 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1369 multiclass VOP2_Real_dpp<GFXGen Gen, bits<6> op> {
1371 def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), Gen>;
1374 multiclass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> {
1376 def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(NAME#"_e32"), Gen>;
1379 //===------------------------- VOP2 (with name) -------------------------===//
1380 multiclass VOP2_Real_e32_with_name<GFXGen Gen, bits<6> op, string opName,
1383 def _e32#Gen.Suffix :
1384 VOP2_Real_Gen<ps, Gen, asmName>,
1385 VOP2e<op{5-0}, ps.Pfl> {
1390 multiclass VOP2_Real_e64_with_name<GFXGen Gen, bits<6> op, string opName,
1393 def _e64#Gen.Suffix :
1394 VOP3_Real_Gen<ps, Gen>,
1395 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, ps.Pfl> {
1400 multiclass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName,
1404 def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen> {
1408 multiclass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName,
1412 def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {
1417 //===------------------------------ VOP2be ------------------------------===//
1418 multiclass VOP2be_Real_e32<GFXGen Gen, bits<6> op, string opName, string asmName> {
1420 def _e32#Gen.Suffix :
1421 VOP2_Real_Gen<ps, Gen>,
1422 VOP2e<op{5-0}, ps.Pfl> {
1426 multiclass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName> {
1428 def _dpp#Gen.Suffix :
1429 VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen, asmName> {
1434 def _dpp_w32#Gen.Suffix :
1440 let AssemblerPredicate = Gen.AssemblerPredicate;
1441 let DecoderNamespace = Gen.DecoderNamespace;
1444 def _dpp_w64#Gen.Suffix :
1450 let AssemblerPredicate = Gen.AssemblerPredicate;
1451 let DecoderNamespace = Gen.DecoderNamespace;
1454 multiclass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> {
1456 def _dpp8#Gen.Suffix :
1457 VOP2_DPP8_Gen<op, !cast<VOP2_Pseudo>(opName#"_e32"), Gen> {
1462 def _dpp8_w32#Gen.Suffix :
1468 let AssemblerPredicate = Gen.AssemblerPredicate;
1469 let DecoderNamespace = Gen.DecoderNamespace;
1472 def _dpp8_w64#Gen.Suffix :
1478 let AssemblerPredicate = Gen.AssemblerPredicate;
1479 let DecoderNamespace = Gen.DecoderNamespace;
1484 multiclass VOP2_Realtriple_e64<GFXGen Gen, bits<6> op> {
1485 defm NAME : VOP3_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME> ;
1488 multiclass VOP2_Realtriple_e64_with_name<GFXGen Gen, bits<6> op, string opName,
1490 defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 0, 0, op{5-0}}, opName, asmName> ;
1493 multiclass VOP2be_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :
1494 VOP2be_Real_e32<Gen, op, opName, asmName>,
1495 VOP3be_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>,
1496 VOP2be_Real_dpp<Gen, op, opName, asmName>,
1497 VOP2be_Real_dpp8<Gen, op, opName, asmName>;
1500 multiclass VOP2e_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :
1501 VOP2_Real_e32<Gen, op>,
1502 VOP2_Realtriple_e64<Gen, op>,
1503 VOP2be_Real_dpp<Gen, op, opName, asmName>,
1504 VOP2be_Real_dpp8<Gen, op, opName, asmName>;
1506 multiclass VOP2Only_Real<GFXGen Gen, bits<6> op> :
1507 VOP2Only_Real_e32<Gen, op>,
1508 VOP2_Real_dpp<Gen, op>,
1509 VOP2_Real_dpp8<Gen, op>;
1511 multiclass VOP2_Real_FULL<GFXGen Gen, bits<6> op> :
1512 VOP2_Realtriple_e64<Gen, op>,
1513 VOP2_Real_e32<Gen, op>,
1514 VOP2_Real_dpp<Gen, op>,
1515 VOP2_Real_dpp8<Gen, op>;
1517 multiclass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName,
1519 defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName, isSingle>,
1520 VOP2_Real_dpp_with_name<Gen, op, opName, asmName>,
1521 VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>;
1523 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
1524 let AssemblerPredicate = Gen.AssemblerPredicate;
1528 multiclass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName,
1530 VOP2_Realtriple_e64_with_name<Gen, op, opName, asmName>,
1531 VOP2_Real_NO_VOP3_with_name<Gen, op, opName, asmName>;
1533 multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
1535 defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>,
1536 VOP2_Real_e64_with_name<Gen, op, opName, asmName>;
1538 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
1539 let AssemblerPredicate = Gen.AssemblerPredicate;
1543 multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
1544 defm NAME : VOP2_Real_e32<Gen, op>,
1545 VOP2_Real_e64<Gen, op>;
1546 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {
1547 let AssemblerPredicate = Gen.AssemblerPredicate;
1551 //===----------------------------------------------------------------------===//
1553 //===----------------------------------------------------------------------===//
1613 //===----------------------------------------------------------------------===//
1615 //===----------------------------------------------------------------------===//
1741 //===----------------------------------------------------------------------===//
1743 //===----------------------------------------------------------------------===//
1746 //===------------------------------- VOP2 -------------------------------===//
1750 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1756 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
1764 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1769 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1775 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1786 //===------------------------- VOP2 (with name) -------------------------===//
1791 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1800 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1811 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1833 //===------------------------------ VOP2be ------------------------------===//
1837 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1845 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1855 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1862 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1871 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1927 //===----------------------------- VOP3Only -----------------------------===//
1936 //===---------------------------- VOP3beOnly ----------------------------===//
2013 // VOP2 no carry-in, carry-out.
2021 // VOP2 carry-in, carry-out.
2043 // VOP3 carry-out.
2059 //===----------------------------------------------------------------------===//
2061 //===----------------------------------------------------------------------===//
2067 let Inst{8-0} = 0xfa; //dpp
2068 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
2069 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
2070 let Inst{30-25} = op;
2078 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2083 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2088 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>;
2093 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
2098 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
2204 //===----------------------------------------------------------------------===//
2206 //===----------------------------------------------------------------------===//
2212 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2217 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> {
2225 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2244 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
2252 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2259 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2267 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
2273 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
2280 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
2300 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
2306 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
2313 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
2329 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2332 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
2336 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
2436 // Aliases to simplify matching of floating-point instructions that
2480 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2491 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;