Lines Matching defs:STI
168 /// \returns True if \p STI is AMDHSA.
169 bool isHsaAbi(const MCSubtargetInfo &STI) {
170 return STI.getTargetTriple().getOS() == Triple::AMDHSA;
767 AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)
768 : STI(STI), XnackSetting(TargetIDSetting::Any),
770 if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
772 if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
860 auto TargetTriple = STI.getTargetTriple();
861 auto Version = getIsaVersion(STI.getCPU());
873 Processor = STI.getCPU().str();
880 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) {
899 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
900 if (STI->getFeatureBits().test(FeatureWavefrontSize16))
902 if (STI->getFeatureBits().test(FeatureWavefrontSize32))
908 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
910 if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
912 if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
918 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
924 unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI) {
925 if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
927 if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
932 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
936 if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
943 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
946 if (STI->getTargetTriple().getArch() != Triple::amdgcn)
948 unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
949 unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
956 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
962 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
966 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
968 if (isGFX90A(*STI))
970 if (!isGFX10Plus(*STI))
972 return hasGFX10_3Insts(*STI) ? 16 : 20;
975 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
977 return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
978 getEUsPerCU(STI));
981 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {
985 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {
990 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
992 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
995 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
996 IsaVersion Version = getIsaVersion(STI->getCPU());
998 return getAddressableNumSGPRs(STI);
1004 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI) {
1008 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
1009 IsaVersion Version = getIsaVersion(STI->getCPU());
1015 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI) {
1016 if (STI->getFeatureBits().test(FeatureSGPRInitBug))
1019 IsaVersion Version = getIsaVersion(STI->getCPU());
1027 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1030 IsaVersion Version = getIsaVersion(STI->getCPU());
1034 if (WavesPerEU >= getMaxWavesPerEU(STI))
1037 unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
1038 if (STI->getFeatureBits().test(FeatureTrapHandler))
1040 MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
1041 return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
1044 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
1048 unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
1049 IsaVersion Version = getIsaVersion(STI->getCPU());
1054 unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
1055 if (STI->getFeatureBits().test(FeatureTrapHandler))
1057 MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
1061 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1067 IsaVersion Version = getIsaVersion(STI->getCPU());
1079 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
1086 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1088 return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
1089 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
1097 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
1099 return getGranulatedNumRegisterBlocks(NumSGPRs, getSGPREncodingGranule(STI)) -
1103 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
1105 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1110 STI->getFeatureBits().test(FeatureWavefrontSize32);
1112 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1115 if (hasGFX10_3Insts(*STI))
1121 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
1123 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1128 STI->getFeatureBits().test(FeatureWavefrontSize32);
1133 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
1134 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1136 if (!isGFX10Plus(*STI))
1138 bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32);
1139 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1144 unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { return 256; }
1146 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) {
1147 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1149 return getAddressableNumArchVGPRs(STI);
1152 unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
1154 return getNumWavesPerEUWithNumVGPRs(NumVGPRs, getVGPRAllocGranule(STI),
1155 getMaxWavesPerEU(STI),
1156 getTotalNumVGPRs(STI));
1195 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1198 unsigned MaxWavesPerEU = getMaxWavesPerEU(STI);
1202 unsigned TotNumVGPRs = getTotalNumVGPRs(STI);
1203 unsigned AddrsableNumVGPRs = getAddressableNumVGPRs(STI);
1204 unsigned Granule = getVGPRAllocGranule(STI);
1210 unsigned MinWavesPerEU = getNumWavesPerEUWithNumVGPRs(STI, AddrsableNumVGPRs);
1212 return getMinNumVGPRs(STI, MinWavesPerEU);
1219 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1222 unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
1223 getVGPRAllocGranule(STI));
1224 unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
1228 unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
1231 NumVGPRs, getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
1235 unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
1239 NumVGPRs, getVGPRAllocGranule(STI, EnableWavefrontSize32));
1244 const MCSubtargetInfo *STI) {
1245 IsaVersion Version = getIsaVersion(STI->getCPU());
1253 if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
1272 S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
1556 const MCSubtargetInfo &STI) {
1560 if (Op.isSupported(STI))
1569 const MCSubtargetInfo &STI) {
1574 if (!Op.isSupported(STI))
1588 const MCSubtargetInfo &STI) {
1591 if (Op.isSupported(STI)) {
1612 const MCSubtargetInfo &STI) {
1617 if (!Op.isSupported(STI)) {
1637 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI) {
1640 Default = getDefaultCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, STI);
1645 const MCSubtargetInfo &STI) {
1647 HasNonDefaultVal, STI);
1651 bool &IsDefault, const MCSubtargetInfo &STI) {
1653 IsDefault, STI);
1657 const MCSubtargetInfo &STI) {
1659 STI);
1756 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1759 return !isGFX11Plus(STI);
1762 return isGFX10Plus(STI);
1765 return isGFX11Plus(STI);
1768 return !isGFX11Plus(STI);
1794 static StringLiteral const *getNfmtLookupTable(const MCSubtargetInfo &STI) {
1795 if (isSI(STI) || isCI(STI))
1797 if (isVI(STI) || isGFX9(STI))
1802 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1803 auto lookupTable = getNfmtLookupTable(STI);
1811 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1813 return getNfmtLookupTable(STI)[Id];
1816 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1820 return isValidNfmt(Nfmt, STI);
1823 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1824 return !getNfmtName(Id, STI).empty();
1836 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI) {
1837 if (isGFX11Plus(STI)) {
1851 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI) {
1852 if(isValidUnifiedFormat(Id, STI))
1853 return isGFX10(STI) ? UfmtSymbolicGFX10[Id] : UfmtSymbolicGFX11[Id];
1857 bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) {
1858 return isGFX10(STI) ? Id <= UfmtGFX10::UFMT_LAST : Id <= UfmtGFX11::UFMT_LAST;
1862 const MCSubtargetInfo &STI) {
1864 if (isGFX11Plus(STI)) {
1878 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1879 return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1882 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI) {
1883 if (isGFX10Plus(STI))
1896 static uint64_t getMsgIdMask(const MCSubtargetInfo &STI) {
1897 return isGFX11Plus(STI) ? ID_MASK_GFX11Plus_ : ID_MASK_PreGFX11_;
1900 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) {
1901 return (MsgId & ~(getMsgIdMask(STI))) == 0;
1904 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1906 assert(isValidMsgId(MsgId, STI));
1911 if (msgRequiresOp(MsgId, STI)) {
1915 return !getMsgOpName(MsgId, OpId, STI).empty();
1922 const MCSubtargetInfo &STI, bool Strict) {
1923 assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1928 if (!isGFX11Plus(STI)) {
1941 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
1943 (!isGFX11Plus(STI) &&
1948 const MCSubtargetInfo &STI) {
1949 return !isGFX11Plus(STI) &&
1955 uint16_t &StreamId, const MCSubtargetInfo &STI) {
1956 MsgId = Val & getMsgIdMask(STI);
1957 if (isGFX11Plus(STI)) {
2058 bool hasXNACK(const MCSubtargetInfo &STI) {
2059 return STI.hasFeature(AMDGPU::FeatureXNACK);
2062 bool hasSRAMECC(const MCSubtargetInfo &STI) {
2063 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2066 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
2067 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2070 bool hasA16(const MCSubtargetInfo &STI) {
2071 return STI.hasFeature(AMDGPU::FeatureA16);
2074 bool hasG16(const MCSubtargetInfo &STI) {
2075 return STI.hasFeature(AMDGPU::FeatureG16);
2078 bool hasPackedD16(const MCSubtargetInfo &STI) {
2079 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
2080 !isSI(STI);
2083 bool hasGDS(const MCSubtargetInfo &STI) {
2084 return STI.hasFeature(AMDGPU::FeatureGDS);
2087 unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) {
2088 auto Version = getIsaVersion(STI.getCPU());
2098 unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI) { return 16; }
2100 bool isSI(const MCSubtargetInfo &STI) {
2101 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2104 bool isCI(const MCSubtargetInfo &STI) {
2105 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2108 bool isVI(const MCSubtargetInfo &STI) {
2109 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2112 bool isGFX9(const MCSubtargetInfo &STI) {
2113 return STI.hasFeature(AMDGPU::FeatureGFX9);
2116 bool isGFX9_GFX10(const MCSubtargetInfo &STI) {
2117 return isGFX9(STI) || isGFX10(STI);
2120 bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI) {
2121 return isGFX9(STI) || isGFX10(STI) || isGFX11(STI);
2124 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI) {
2125 return isVI(STI) || isGFX9(STI) || isGFX10(STI);
2128 bool isGFX8Plus(const MCSubtargetInfo &STI) {
2129 return isVI(STI) || isGFX9Plus(STI);
2132 bool isGFX9Plus(const MCSubtargetInfo &STI) {
2133 return isGFX9(STI) || isGFX10Plus(STI);
2136 bool isNotGFX9Plus(const MCSubtargetInfo &STI) { return !isGFX9Plus(STI); }
2138 bool isGFX10(const MCSubtargetInfo &STI) {
2139 return STI.hasFeature(AMDGPU::FeatureGFX10);
2142 bool isGFX10_GFX11(const MCSubtargetInfo &STI) {
2143 return isGFX10(STI) || isGFX11(STI);
2146 bool isGFX10Plus(const MCSubtargetInfo &STI) {
2147 return isGFX10(STI) || isGFX11Plus(STI);
2150 bool isGFX11(const MCSubtargetInfo &STI) {
2151 return STI.hasFeature(AMDGPU::FeatureGFX11);
2154 bool isGFX11Plus(const MCSubtargetInfo &STI) {
2155 return isGFX11(STI) || isGFX12Plus(STI);
2158 bool isGFX12(const MCSubtargetInfo &STI) {
2159 return STI.getFeatureBits()[AMDGPU::FeatureGFX12];
2162 bool isGFX12Plus(const MCSubtargetInfo &STI) { return isGFX12(STI); }
2164 bool isNotGFX12Plus(const MCSubtargetInfo &STI) { return !isGFX12Plus(STI); }
2166 bool isNotGFX11Plus(const MCSubtargetInfo &STI) {
2167 return !isGFX11Plus(STI);
2170 bool isNotGFX10Plus(const MCSubtargetInfo &STI) {
2171 return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
2174 bool isGFX10Before1030(const MCSubtargetInfo &STI) {
2175 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
2178 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
2179 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2182 bool isGFX10_AEncoding(const MCSubtargetInfo &STI) {
2183 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2186 bool isGFX10_BEncoding(const MCSubtargetInfo &STI) {
2187 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2190 bool hasGFX10_3Insts(const MCSubtargetInfo &STI) {
2191 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2194 bool isGFX10_3_GFX11(const MCSubtargetInfo &STI) {
2195 return isGFX10_BEncoding(STI) && !isGFX12Plus(STI);
2198 bool isGFX90A(const MCSubtargetInfo &STI) {
2199 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2202 bool isGFX940(const MCSubtargetInfo &STI) {
2203 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2206 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
2207 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2210 bool hasMAIInsts(const MCSubtargetInfo &STI) {
2211 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2214 bool hasVOPD(const MCSubtargetInfo &STI) {
2215 return STI.hasFeature(AMDGPU::FeatureVOPD);
2218 bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI) {
2219 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2222 unsigned hasKernargPreload(const MCSubtargetInfo &STI) {
2223 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2289 assert(!isSI(STI)); \
2290 case node: return isCI(STI) ? node##_ci : node##_vi;
2293 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2296 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2299 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2301 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
2302 if (STI.getTargetTriple().getArch() == Triple::r600)
2939 const MCSubtargetInfo &STI) {
2940 return isGFX11Plus(STI)
2943 : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2950 const MCSubtargetInfo &STI) {
2951 return isGFX11Plus(STI) ? getGfx11PlusBufferFormatInfo(Format)
2952 : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)