Lines Matching defs:OpDesc

666 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) {
667   assert(OpDesc.getNumDefs() == Component::DST_NUM);
669   assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1);
670   assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1);
671   auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO);
675   SrcOperandsNum = OpDesc.getNumOperands() - OpDesc.getNumDefs();
678   auto OperandsNum = OpDesc.getNumOperands();
681     if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) {
2956 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) {
2959     int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName);
2963     if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||
2964         OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
2971 bool isDPALU_DPP(const MCInstrDesc &OpDesc) {
2972   return hasAny64BitVGPROperands(OpDesc);