Lines Matching defs:AMDGPU
1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
10 #include "AMDGPU.h"
38 llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
160 namespace AMDGPU {
223 return AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET;
237 return AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET;
248 return AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET;
259 return AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET;
529 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
531 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
549 return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X);
553 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
554 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
555 Opc == AMDGPU::V_MAC_F32_e64_vi ||
556 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
557 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
558 Opc == AMDGPU::V_MAC_F16_e64_vi ||
559 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
560 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
561 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
562 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
563 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
564 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
565 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
566 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
567 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
568 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
569 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
570 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
571 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
572 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
576 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
577 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
578 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
579 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
580 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
581 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
582 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
583 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
587 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
588 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
589 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
590 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
591 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
592 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
593 Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
594 Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
598 return Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
599 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
600 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
601 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
602 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
603 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
604 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
605 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
606 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
607 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
608 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
609 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
610 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
611 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
612 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
613 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
614 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
681 if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) {
1079 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
1089 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
2055 return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
2059 return STI.hasFeature(AMDGPU::FeatureXNACK);
2063 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2067 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2071 return STI.hasFeature(AMDGPU::FeatureA16);
2075 return STI.hasFeature(AMDGPU::FeatureG16);
2079 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
2084 return STI.hasFeature(AMDGPU::FeatureGDS);
2101 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2105 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2109 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2113 return STI.hasFeature(AMDGPU::FeatureGFX9);
2139 return STI.hasFeature(AMDGPU::FeatureGFX10);
2151 return STI.hasFeature(AMDGPU::FeatureGFX11);
2159 return STI.getFeatureBits()[AMDGPU::FeatureGFX12];
2175 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
2179 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2183 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2187 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2191 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2199 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2203 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2207 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2211 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2215 return STI.hasFeature(AMDGPU::FeatureVOPD);
2219 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2223 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2234 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2235 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
2237 Reg == AMDGPU::SCC;
2241 return MRI.getEncodingValue(Reg) & AMDGPU::HWEncoding::IS_HI;
2245 using namespace AMDGPU; \
2323 case AMDGPU::SRC_SHARED_BASE_LO:
2324 case AMDGPU::SRC_SHARED_BASE:
2325 case AMDGPU::SRC_SHARED_LIMIT_LO:
2326 case AMDGPU::SRC_SHARED_LIMIT:
2327 case AMDGPU::SRC_PRIVATE_BASE_LO:
2328 case AMDGPU::SRC_PRIVATE_BASE:
2329 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2330 case AMDGPU::SRC_PRIVATE_LIMIT:
2331 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2333 case AMDGPU::SRC_VCCZ:
2334 case AMDGPU::SRC_EXECZ:
2335 case AMDGPU::SRC_SCC:
2337 case AMDGPU::SGPR_NULL:
2353 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
2354 OpType <= AMDGPU::OPERAND_SRC_LAST;
2360 return OpType >= AMDGPU::OPERAND_KIMM_FIRST &&
2361 OpType <= AMDGPU::OPERAND_KIMM_LAST;
2368 case AMDGPU::OPERAND_REG_IMM_FP32:
2369 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
2370 case AMDGPU::OPERAND_REG_IMM_FP64:
2371 case AMDGPU::OPERAND_REG_IMM_FP16:
2372 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
2373 case AMDGPU::OPERAND_REG_IMM_V2FP16:
2374 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2375 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2376 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
2377 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2378 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
2379 case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
2380 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
2381 case AMDGPU::OPERAND_REG_IMM_V2FP32:
2382 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
2383 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2393 return (OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
2394 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST) ||
2395 (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST &&
2396 OpType <= AMDGPU::OPERAND_REG_INLINE_AC_LAST);
2403 case AMDGPU::SGPR_LO16RegClassID:
2404 case AMDGPU::AGPR_LO16RegClassID:
2406 case AMDGPU::SGPR_32RegClassID:
2407 case AMDGPU::VGPR_32RegClassID:
2408 case AMDGPU::VRegOrLds_32RegClassID:
2409 case AMDGPU::AGPR_32RegClassID:
2410 case AMDGPU::VS_32RegClassID:
2411 case AMDGPU::AV_32RegClassID:
2412 case AMDGPU::SReg_32RegClassID:
2413 case AMDGPU::SReg_32_XM0RegClassID:
2414 case AMDGPU::SRegOrLds_32RegClassID:
2416 case AMDGPU::SGPR_64RegClassID:
2417 case AMDGPU::VS_64RegClassID:
2418 case AMDGPU::SReg_64RegClassID:
2419 case AMDGPU::VReg_64RegClassID:
2420 case AMDGPU::AReg_64RegClassID:
2421 case AMDGPU::SReg_64_XEXECRegClassID:
2422 case AMDGPU::VReg_64_Align2RegClassID:
2423 case AMDGPU::AReg_64_Align2RegClassID:
2424 case AMDGPU::AV_64RegClassID:
2425 case AMDGPU::AV_64_Align2RegClassID:
2427 case AMDGPU::SGPR_96RegClassID:
2428 case AMDGPU::SReg_96RegClassID:
2429 case AMDGPU::VReg_96RegClassID:
2430 case AMDGPU::AReg_96RegClassID:
2431 case AMDGPU::VReg_96_Align2RegClassID:
2432 case AMDGPU::AReg_96_Align2RegClassID:
2433 case AMDGPU::AV_96RegClassID:
2434 case AMDGPU::AV_96_Align2RegClassID:
2436 case AMDGPU::SGPR_128RegClassID:
2437 case AMDGPU::SReg_128RegClassID:
2438 case AMDGPU::VReg_128RegClassID:
2439 case AMDGPU::AReg_128RegClassID:
2440 case AMDGPU::VReg_128_Align2RegClassID:
2441 case AMDGPU::AReg_128_Align2RegClassID:
2442 case AMDGPU::AV_128RegClassID:
2443 case AMDGPU::AV_128_Align2RegClassID:
2445 case AMDGPU::SGPR_160RegClassID:
2446 case AMDGPU::SReg_160RegClassID:
2447 case AMDGPU::VReg_160RegClassID:
2448 case AMDGPU::AReg_160RegClassID:
2449 case AMDGPU::VReg_160_Align2RegClassID:
2450 case AMDGPU::AReg_160_Align2RegClassID:
2451 case AMDGPU::AV_160RegClassID:
2452 case AMDGPU::AV_160_Align2RegClassID:
2454 case AMDGPU::SGPR_192RegClassID:
2455 case AMDGPU::SReg_192RegClassID:
2456 case AMDGPU::VReg_192RegClassID:
2457 case AMDGPU::AReg_192RegClassID:
2458 case AMDGPU::VReg_192_Align2RegClassID:
2459 case AMDGPU::AReg_192_Align2RegClassID:
2460 case AMDGPU::AV_192RegClassID:
2461 case AMDGPU::AV_192_Align2RegClassID:
2463 case AMDGPU::SGPR_224RegClassID:
2464 case AMDGPU::SReg_224RegClassID:
2465 case AMDGPU::VReg_224RegClassID:
2466 case AMDGPU::AReg_224RegClassID:
2467 case AMDGPU::VReg_224_Align2RegClassID:
2468 case AMDGPU::AReg_224_Align2RegClassID:
2469 case AMDGPU::AV_224RegClassID:
2470 case AMDGPU::AV_224_Align2RegClassID:
2472 case AMDGPU::SGPR_256RegClassID:
2473 case AMDGPU::SReg_256RegClassID:
2474 case AMDGPU::VReg_256RegClassID:
2475 case AMDGPU::AReg_256RegClassID:
2476 case AMDGPU::VReg_256_Align2RegClassID:
2477 case AMDGPU::AReg_256_Align2RegClassID:
2478 case AMDGPU::AV_256RegClassID:
2479 case AMDGPU::AV_256_Align2RegClassID:
2481 case AMDGPU::SGPR_288RegClassID:
2482 case AMDGPU::SReg_288RegClassID:
2483 case AMDGPU::VReg_288RegClassID:
2484 case AMDGPU::AReg_288RegClassID:
2485 case AMDGPU::VReg_288_Align2RegClassID:
2486 case AMDGPU::AReg_288_Align2RegClassID:
2487 case AMDGPU::AV_288RegClassID:
2488 case AMDGPU::AV_288_Align2RegClassID:
2490 case AMDGPU::SGPR_320RegClassID:
2491 case AMDGPU::SReg_320RegClassID:
2492 case AMDGPU::VReg_320RegClassID:
2493 case AMDGPU::AReg_320RegClassID:
2494 case AMDGPU::VReg_320_Align2RegClassID:
2495 case AMDGPU::AReg_320_Align2RegClassID:
2496 case AMDGPU::AV_320RegClassID:
2497 case AMDGPU::AV_320_Align2RegClassID:
2499 case AMDGPU::SGPR_352RegClassID:
2500 case AMDGPU::SReg_352RegClassID:
2501 case AMDGPU::VReg_352RegClassID:
2502 case AMDGPU::AReg_352RegClassID:
2503 case AMDGPU::VReg_352_Align2RegClassID:
2504 case AMDGPU::AReg_352_Align2RegClassID:
2505 case AMDGPU::AV_352RegClassID:
2506 case AMDGPU::AV_352_Align2RegClassID:
2508 case AMDGPU::SGPR_384RegClassID:
2509 case AMDGPU::SReg_384RegClassID:
2510 case AMDGPU::VReg_384RegClassID:
2511 case AMDGPU::AReg_384RegClassID:
2512 case AMDGPU::VReg_384_Align2RegClassID:
2513 case AMDGPU::AReg_384_Align2RegClassID:
2514 case AMDGPU::AV_384RegClassID:
2515 case AMDGPU::AV_384_Align2RegClassID:
2517 case AMDGPU::SGPR_512RegClassID:
2518 case AMDGPU::SReg_512RegClassID:
2519 case AMDGPU::VReg_512RegClassID:
2520 case AMDGPU::AReg_512RegClassID:
2521 case AMDGPU::VReg_512_Align2RegClassID:
2522 case AMDGPU::AReg_512_Align2RegClassID:
2523 case AMDGPU::AV_512RegClassID:
2524 case AMDGPU::AV_512_Align2RegClassID:
2526 case AMDGPU::SGPR_1024RegClassID:
2527 case AMDGPU::SReg_1024RegClassID:
2528 case AMDGPU::VReg_1024RegClassID:
2529 case AMDGPU::AReg_1024RegClassID:
2530 case AMDGPU::VReg_1024_Align2RegClassID:
2531 case AMDGPU::AReg_1024_Align2RegClassID:
2532 case AMDGPU::AV_1024RegClassID:
2533 case AMDGPU::AV_1024_Align2RegClassID:
2728 case AMDGPU::OPERAND_REG_IMM_V2INT16:
2729 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2730 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2732 case AMDGPU::OPERAND_REG_IMM_V2FP16:
2733 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2734 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
2736 case AMDGPU::OPERAND_REG_IMM_V2BF16:
2737 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
2738 case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
2899 if (AMDGPU::isGFX10(ST))
2902 if (AMDGPU::isGFX12(ST))
2963 if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||
2964 OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
2980 } // namespace AMDGPU
2983 const AMDGPU::IsaInfo::TargetIDSetting S) {
2985 case (AMDGPU::IsaInfo::TargetIDSetting::Unsupported):
2988 case (AMDGPU::IsaInfo::TargetIDSetting::Any):
2991 case (AMDGPU::IsaInfo::TargetIDSetting::Off):
2994 case (AMDGPU::IsaInfo::TargetIDSetting::On):