Lines Matching defs:ValueReg

1216                                            unsigned ValueReg, bool IsKill) {
1230   unsigned Dst = IsStore ? Reg : ValueReg;
1231   unsigned Src = IsStore ? ValueReg : Reg;
1234   if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) {
1331     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1349   const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);
1543             ? ValueReg
1544             : Register(getSubReg(ValueReg,
1577              ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
1578              : ValueReg;
1583         MIB.addReg(ValueReg, RegState::ImplicitDefine);
1593         MIB.addReg(ValueReg, RegState::Implicit | State);
1605       SubReg = Register(getSubReg(ValueReg,
1626           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
1679       MIB.addReg(ValueReg, RegState::ImplicitDefine);
1689       MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);