Lines Matching defs:SB
1727 void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
1731 MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo();
1735 FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF)
1737 : getFrameRegister(SB.MF);
1740 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SB.MF, Index);
1741 MachineMemOperand *MMO = SB.MF.getMachineMemOperand(
1743 SB.EltSize, Alignment);
1748 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
1749 FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
1753 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
1754 FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
1756 SB.MFI.addToSpilledVGPRs(1);
1764 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1767 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index)
1768 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index);
1773 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&
1774 SB.SuperReg != SB.MFI.getFrameOffsetReg()));
1778 assert(SB.NumSubRegs == VGPRSpills.size() &&
1781 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1783 SB.NumSubRegs == 1
1784 ? SB.SuperReg
1785 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1789 bool IsLastSubreg = i == SB.NumSubRegs - 1;
1790 bool UseKill = SB.IsKill && IsLastSubreg;
1795 auto MIB = BuildMI(*SB.MBB, MI, SB.DL,
1796 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR)
1807 if (IsFirstSubreg && SB.NumSubRegs > 1) {
1810 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1813 if (SB.NumSubRegs > 1 && (IsFirstSubreg || IsLastSubreg))
1814 MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);
1821 SB.prepare();
1823 // SubReg carries the "Kill" flag when SubReg == SB.SuperReg.
1824 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1827 auto PVD = SB.getPerVGPRData();
1834 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1837 SB.NumSubRegs == 1
1838 ? SB.SuperReg
1839 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1842 BuildMI(*SB.MBB, MI, SB.DL,
1843 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), SB.TmpVGPR)
1846 .addReg(SB.TmpVGPR, TmpVGPRFlags);
1858 if (SB.NumSubRegs > 1) {
1859 // The last implicit use of the SB.SuperReg carries the "Kill" flag.
1861 if (i + 1 == SB.NumSubRegs)
1862 SuperKillState |= getKillRegState(SB.IsKill);
1863 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
1868 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false);
1871 SB.restore();
1875 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs);
1878 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);
1887 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
1890 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index)
1891 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index);
1897 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) {
1899 SB.NumSubRegs == 1
1900 ? SB.SuperReg
1901 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1904 auto MIB = BuildMI(*SB.MBB, MI, SB.DL,
1905 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)
1908 if (SB.NumSubRegs > 1 && i == 0)
1909 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1918 SB.prepare();
1921 auto PVD = SB.getPerVGPRData();
1925 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true);
1929 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1932 SB.NumSubRegs == 1
1933 ? SB.SuperReg
1934 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1937 auto MIB = BuildMI(*SB.MBB, MI, SB.DL,
1938 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg)
1939 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))
1941 if (SB.NumSubRegs > 1 && i == 0)
1942 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1952 SB.restore();
1958 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);
1966 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0,
1968 SB.prepare();
1969 // Generate the spill of SGPR to SB.TmpVGPR.
1970 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1971 auto PVD = SB.getPerVGPRData();
1976 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
1979 SB.NumSubRegs == 1
1980 ? SB.SuperReg
1981 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
1984 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32),
1985 SB.TmpVGPR)
1988 .addReg(SB.TmpVGPR, TmpVGPRFlags);
1992 if (SB.NumSubRegs > 1) {
1993 // The last implicit use of the SB.SuperReg carries the "Kill" flag.
1995 if (i + 1 == SB.NumSubRegs)
1996 SuperKillState |= getKillRegState(SB.IsKill);
1997 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);
2005 SB.setMI(&RestoreMBB, MI);
2006 // Generate the restore of SGPR from SB.TmpVGPR.
2011 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs);
2014 SB.NumSubRegs == 1
2015 ? SB.SuperReg
2016 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));
2018 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32),
2020 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg))
2022 if (SB.NumSubRegs > 1 && i == 0)
2023 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
2026 SB.restore();
2028 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs);