Lines Matching defs:LoadStoreOp

1266   int LoadStoreOp = IsStore ?
1268   if (LoadStoreOp == -1)
1276       BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
1293                                           unsigned LoadStoreOp,
1295   bool IsStore = TII->get(LoadStoreOp).mayStore();
1296   bool HasVAddr = AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::vaddr);
1298       !HasVAddr && !AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::saddr);
1302     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1306     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1310     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1314     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1322     LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1324     LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1326   return LoadStoreOp;
1331     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1341   const MCInstrDesc *Desc = &TII->get(LoadStoreOp);
1343   bool IsFlat = TII->isFLATScratch(LoadStoreOp);
1368     LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1369     Desc = &TII->get(LoadStoreOp);
1504     assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0
1508       LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1511       LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1514     Desc = &TII->get(LoadStoreOp);
1521       LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1523     Desc = &TII->get(LoadStoreOp);
1526       int NewLoadStoreOp = IsStore ? getOffenMUBUFStore(LoadStoreOp)
1527                                    : getOffenMUBUFLoad(LoadStoreOp);
1607       unsigned Opc = getFlatScratchSpillOpcode(TII, LoadStoreOp, RemEltSize);