Lines Matching defs:IsKill

84   bool IsKill;
120                    bool IsKill, int Index, RegScavenger *RS)
121       : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),
227                                     /*IsKill*/ false);
251                                   /*IsKill*/ false);
263                                   /*IsKill*/ false);
301                                   /*IsKill*/ false);
1216                                            unsigned ValueReg, bool IsKill) {
1240                        .addReg(Src, getKillRegState(IsKill));
1248                  .addReg(Src, getKillRegState(IsKill));
1331     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1554       SrcDstRegState |= getKillRegState(IsKill);
1579       auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill);
1624                            .addReg(SubReg, getKillRegState(IsKill));
1645             .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1729                                              bool IsKill) const {
1753     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
1790       bool UseKill = SB.IsKill && IsLastSubreg;
1824     unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1862             SuperKillState |= getKillRegState(SB.IsKill);
1970   unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
1996           SuperKillState |= getKillRegState(SB.IsKill);