Lines Matching defs:EltSize

99   unsigned EltSize = 4;
126     SplitParts = TRI.getRegSplitParts(RC, EltSize);
1294                                           unsigned EltSize) {
1300   switch (EltSize) {
1356   unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1357   unsigned NumSubRegs = RegWidth / EltSize;
1358   unsigned Size = NumSubRegs * EltSize;
1364   int64_t MaxOffset = Offset + Size + RemSize - EltSize;
1367   if (IsFlat && EltSize > 4) {
1368     LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1375   assert((IsFlat || ((Offset % EltSize) == 0)) &&
1478     // We currently only support spilling VGPRs to EltSize boundaries, meaning
1518        ++i, RegOffset += EltSize) {
1520       EltSize = RemSize;
1521       LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1541     unsigned NumRegs = EltSize / 4;
1564     unsigned RemEltSize = EltSize;
1572     for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS,
1575       bool IsSubReg = e > 1 || EltSize > 4;
1601     if (RemEltSize != EltSize) { // Partially spilled to AGPRs
1602       assert(IsFlat && EltSize > 4);
1614       assert(EltSize == 4);
1743       SB.EltSize, Alignment);
1749                         FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
1754                         FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
2985                                                    unsigned EltSize) const {
2990   const unsigned EltDWORDs = EltSize / 4;