Lines Matching full:flow

14 /// successive if-then (with a flow block to do predicate inversion). Consider a
23 ///    bb.flow:
30 ///  As register allocator has no idea of the thread-control-flow, it will just
40 ///  through inserting a phi-node in bb.flow saying that %a is undef when coming
104   void collectElseRegionBlocks(MachineBasicBlock *Flow,
109   collectCandidateRegisters(MachineBasicBlock *If, MachineBasicBlock *Flow,
124                                    MachineBasicBlock *Flow) const;
127       Register Reg, Register NewReg, MachineBasicBlock *Flow,
133                     MachineBasicBlock *Flow, MachineBasicBlock *Endif,
172 // Check whether the MBB is a else flow block and get the branching target which
184     MachineBasicBlock *Flow, MachineBasicBlock *Endif,
186   assert(Flow != Endif);
192       if (Pred != Flow && !Blocks.contains(Pred))
223     MachineBasicBlock *If, MachineBasicBlock *Flow, MachineBasicBlock *Endif,
272       if (Pred == Flow)
307       if (UseMBB == Flow || UseMBB == Endif) {
312         // The register is live through the path If->Flow or Flow->Endif.
314         if ((UseMBB == Flow && IncomingMBB != If) ||
315             (UseMBB == Endif && IncomingMBB == Flow))
401     Register Reg, MachineBasicBlock *If, MachineBasicBlock *Flow) const {
405   // Collect all successors until we see the flow block, where we should
410       if (Succ != Flow && !Blocks.contains(Succ)) {
470     Register Reg, Register NewReg, MachineBasicBlock *Flow,
500     Register Reg, MachineBasicBlock *If, MachineBasicBlock *Flow,
509   MachineInstrBuilder PHI = BuildMI(*Flow, Flow->getFirstNonPHI(), DebugLoc(),
511   for (auto *Pred : Flow->predecessors()) {
544   // The optimized Reg is not alive through Flow blocks anymore.
546   OldVarInfo.AliveBlocks.reset(Flow->getNumber());
548   updateLiveRangeInElseRegion(Reg, NewReg, Flow, Endif, ElseBlocks);
549   updateLiveRangeInThenRegion(Reg, If, Flow);
659         // Skip unexpected control flow.