Lines Matching defs:TII
138 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
140 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
142 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
144 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
147 const SIInstrInfo *TII, Status InstrMode);
165 const SIInstrInfo *TII) {
166 if (TII->usesFPDPRounding(MI) ||
178 if (TII->getSubtarget().hasTrue16BitInsts()) {
181 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64));
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32));
195 if (TII->getSubtarget().hasTrue16BitInsts()) {
198 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64));
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32));
223 const SIInstrInfo *TII, Status InstrMode) {
229 BuildMI(MBB, MI, nullptr, TII->get(AMDGPU::S_SETREG_IMM32_B32))
258 const SIInstrInfo *TII) {
269 Status InstrMode = getInstructionMode(MI, TII);
277 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm();
287 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
295 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm();
321 insertSetreg(MBB, InsertionPoint, TII,
345 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
356 const SIInstrInfo *TII) {
420 const SIInstrInfo *TII) {
426 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta);
428 insertSetreg(MBB, &MBB.instr_front(), TII, Delta);
443 const SIInstrInfo *TII = ST.getInstrInfo();
450 processBlockPhase1(BB, TII);
458 processBlockPhase2(*Phase2List.front(), TII);
465 processBlockPhase3(BB, TII);