Lines Matching defs:TryCand

140                     SISchedulerCandidate &TryCand,
144     TryCand.Reason = Reason;
157                        SISchedulerCandidate &TryCand,
161     TryCand.Reason = Reason;
190                                           SISchedCandidate &TryCand) {
193     TryCand.Reason = NodeOrder;
198       SISched::tryLess(TryCand.SGPRUsage, Cand.SGPRUsage,
199                        TryCand, Cand, RegUsage))
217   if (SISched::tryLess(TryCand.HasLowLatencyNonWaitedParent,
219                        TryCand, Cand, SIScheduleCandReason::Depth))
222   if (SISched::tryGreater(TryCand.IsLowLatency, Cand.IsLowLatency,
223                           TryCand, Cand, SIScheduleCandReason::Depth))
226   if (TryCand.IsLowLatency &&
227       SISched::tryLess(TryCand.LowLatencyOffset, Cand.LowLatencyOffset,
228                        TryCand, Cand, SIScheduleCandReason::Depth))
231   if (SISched::tryLess(TryCand.VGPRUsage, Cand.VGPRUsage,
232                        TryCand, Cand, RegUsage))
236   if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
237     TryCand.Reason = NodeOrder;
245     SISchedCandidate TryCand;
249     TryCand.SU = SU;
251     TryCand.SGPRUsage = pressure[AMDGPU::RegisterPressureSets::SReg_32];
252     TryCand.VGPRUsage = pressure[AMDGPU::RegisterPressureSets::VGPR_32];
253     TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum];
254     TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum];
255     TryCand.HasLowLatencyNonWaitedParent =
257     tryCandidateTopDown(TopCand, TryCand);
258     if (TryCand.Reason != NoCand)
259       TopCand.setBest(TryCand);
1519                                                    SIBlockSchedCandidate &TryCand) {
1521     TryCand.Reason = NodeOrder;
1526   if (SISched::tryLess(TryCand.LastPosHighLatParentScheduled,
1527                  Cand.LastPosHighLatParentScheduled, TryCand, Cand, Latency))
1530   if (SISched::tryGreater(TryCand.IsHighLatency, Cand.IsHighLatency,
1531                           TryCand, Cand, Latency))
1533   if (TryCand.IsHighLatency && SISched::tryGreater(TryCand.Height, Cand.Height,
1534                                                    TryCand, Cand, Depth))
1536   if (SISched::tryGreater(TryCand.NumHighLatencySuccessors,
1538                           TryCand, Cand, Successor))
1544                                                     SIBlockSchedCandidate &TryCand) {
1546     TryCand.Reason = NodeOrder;
1550   if (SISched::tryLess(TryCand.VGPRUsageDiff > 0, Cand.VGPRUsageDiff > 0,
1551                        TryCand, Cand, RegUsage))
1553   if (SISched::tryGreater(TryCand.NumSuccessors > 0,
1555                           TryCand, Cand, Successor))
1557   if (SISched::tryGreater(TryCand.Height, Cand.Height, TryCand, Cand, Depth))
1559   if (SISched::tryLess(TryCand.VGPRUsageDiff, Cand.VGPRUsageDiff,
1560                        TryCand, Cand, RegUsage))
1593     SIBlockSchedCandidate TryCand;
1594     TryCand.Block = *I;
1595     TryCand.IsHighLatency = TryCand.Block->isHighLatencyBlock();
1596     TryCand.VGPRUsageDiff =
1597       checkRegUsageImpact(TryCand.Block->getInRegs(),
1598           TryCand.Block->getOutRegs())[AMDGPU::RegisterPressureSets::VGPR_32];
1599     TryCand.NumSuccessors = TryCand.Block->getSuccs().size();
1600     TryCand.NumHighLatencySuccessors =
1601       TryCand.Block->getNumHighLatencySuccessors();
1602     TryCand.LastPosHighLatParentScheduled =
1604          LastPosHighLatencyParentScheduled[TryCand.Block->getID()] -
1606     TryCand.Height = TryCand.Block->Height;
1610       if (!tryCandidateRegUsage(Cand, TryCand) &&
1612         tryCandidateLatency(Cand, TryCand);
1614       if (!tryCandidateLatency(Cand, TryCand))
1615         tryCandidateRegUsage(Cand, TryCand);
1617     if (TryCand.Reason != NoCand) {
1618       Cand.setBest(TryCand);