Lines Matching defs:TRI
191 const SIRegisterInfo &TRI) {
193 ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
200 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
207 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
213 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
215 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
222 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
229 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
235 Register SIMachineFunctionInfo::addPrivateSegmentSize(const SIRegisterInfo &TRI) {
241 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
242 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
255 const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
264 TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);
325 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
329 TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
368 const SIRegisterInfo *TRI = ST.getRegisterInfo();
375 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF,
470 const SIRegisterInfo *TRI = ST.getRegisterInfo();
476 OtherUsedRegs.resize(TRI->getNumRegs());
479 TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
505 MRI.reserveReg(*NextSpillReg, TRI);
558 const SIRegisterInfo &TRI) {
563 MFI.CreateStackObject(TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
564 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
609 const TargetRegisterInfo &TRI) {
613 OS << printReg(Reg, &TRI);
620 const TargetRegisterInfo &TRI) {
632 OS << printReg(Arg.getRegister(), &TRI);
672 const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI,
684 ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
685 FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
686 StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
689 ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
694 WWMReservedRegs.push_back(regToString(Reg, TRI));
697 LongBranchReservedReg = regToString(MFI.getLongBranchReservedReg(), TRI);
699 VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI);
702 SGPRForEXECCopy = regToString(MFI.getSGPRForEXECCopy(), TRI);