Lines Matching defs:ST
46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
47 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
48 WavesPerEU = ST.getWavesPerEU(F);
49 MaxNumWorkGroups = ST.getMaxNumWorkGroups(F);
52 Occupancy = ST.computeOccupancy(F, getLDSSize());
67 MayNeedAGPRs = ST.hasMAIInsts();
89 if (!ST.enableFlatScratch()) {
102 MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
105 if (ST.hasGFX90AInsts() &&
106 ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
113 ST.hasArchitectedSGPRs())) {
129 ST.getMaxWorkitemID(F, 1) != 0)
133 ST.getMaxWorkitemID(F, 2) != 0)
146 if (!ST.flatScratchIsArchitected()) {
150 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
170 if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
172 AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
185 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186 limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
367 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
368 const SIRegisterInfo *TRI = ST.getRegisterInfo();
410 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
412 unsigned WaveSize = ST.getWavefrontSize();
421 assert(ST.getRegisterInfo()->spillSGPRToVGPR() &&
451 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
453 assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
470 const SIRegisterInfo *TRI = ST.getRegisterInfo();
589 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
590 if (!ST.isAmdPalOS())
593 if (ST.hasMergedShaders()) {