Lines Matching defs:STM
202 const GCNSubtarget *STM = nullptr;
790 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);
1120 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,
1126 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));
1138 return STM.hasScalarDwordx3Loads();
1184 if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))
1214 offsetsCanBeCombined(CI, *STM, Paired, true);
1276 if (STM->ldsRequiresM0Init())
1282 if (STM->ldsRequiresM0Init())
1349 if (STM->ldsRequiresM0Init())
1356 if (STM->ldsRequiresM0Init())
1561 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);
1604 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);
1730 STM->isXNACKEnabled() && MMO->getAlign().value() < Width * 4;
2087 if (!STM->hasFlatInstOffsets() || !SIInstrInfo::isFLAT(MI))
2160 static_cast<const SITargetLowering *>(STM->getTargetLowering());
2466 STM = &MF.getSubtarget<GCNSubtarget>();
2467 if (!STM->loadStoreOptEnabled())
2470 TII = STM->getInstrInfo();