Lines Matching defs:Opcode
104 static BranchPredicate getBranchPredicate(unsigned Opcode);
133 unsigned Opcode) const;
136 unsigned Opcode) const;
139 unsigned Opcode, bool Swap = false) const;
142 unsigned Opcode,
158 unsigned Opcode,
412 bool isSALU(uint16_t Opcode) const {
413 return get(Opcode).TSFlags & SIInstrFlags::SALU;
420 bool isVALU(uint16_t Opcode) const {
421 return get(Opcode).TSFlags & SIInstrFlags::VALU;
428 bool isImage(uint16_t Opcode) const {
429 return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
436 bool isVMEM(uint16_t Opcode) const {
437 return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
444 bool isSOP1(uint16_t Opcode) const {
445 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
452 bool isSOP2(uint16_t Opcode) const {
453 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
460 bool isSOPC(uint16_t Opcode) const {
461 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
468 bool isSOPK(uint16_t Opcode) const {
469 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
476 bool isSOPP(uint16_t Opcode) const {
477 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
484 bool isPacked(uint16_t Opcode) const {
485 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
492 bool isVOP1(uint16_t Opcode) const {
493 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
500 bool isVOP2(uint16_t Opcode) const {
501 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
508 bool isVOP3(uint16_t Opcode) const {
509 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
516 bool isSDWA(uint16_t Opcode) const {
517 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
524 bool isVOPC(uint16_t Opcode) const {
525 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
532 bool isMUBUF(uint16_t Opcode) const {
533 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
540 bool isMTBUF(uint16_t Opcode) const {
541 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
548 bool isSMRD(uint16_t Opcode) const {
549 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
558 bool isDS(uint16_t Opcode) const {
559 return get(Opcode).TSFlags & SIInstrFlags::DS;
566 bool isLDSDMA(uint16_t Opcode) {
567 return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode));
574 bool isGWS(uint16_t Opcode) const {
575 return get(Opcode).TSFlags & SIInstrFlags::GWS;
578 bool isAlwaysGDS(uint16_t Opcode) const;
584 bool isMIMG(uint16_t Opcode) const {
585 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
592 bool isVIMAGE(uint16_t Opcode) const {
593 return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
600 bool isVSAMPLE(uint16_t Opcode) const {
601 return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
608 bool isGather4(uint16_t Opcode) const {
609 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
623 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
624 auto Flags = get(Opcode).TSFlags;
632 bool isFLATGlobal(uint16_t Opcode) const {
633 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
640 bool isFLATScratch(uint16_t Opcode) const {
641 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
645 bool isFLAT(uint16_t Opcode) const {
646 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
661 bool isEXP(uint16_t Opcode) const {
662 return get(Opcode).TSFlags & SIInstrFlags::EXP;
669 bool isAtomicNoRet(uint16_t Opcode) const {
670 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
677 bool isAtomicRet(uint16_t Opcode) const {
678 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
686 bool isAtomic(uint16_t Opcode) const {
687 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
699 bool isWQM(uint16_t Opcode) const {
700 return get(Opcode).TSFlags & SIInstrFlags::WQM;
707 bool isDisableWQM(uint16_t Opcode) const {
708 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
722 bool isVGPRSpill(uint16_t Opcode) const {
723 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
724 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
725 (isSpill(Opcode) && isVALU(Opcode));
734 bool isSGPRSpill(uint16_t Opcode) const {
735 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
736 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
737 (isSpill(Opcode) && isSALU(Opcode));
740 bool isSpill(uint16_t Opcode) const {
741 return get(Opcode).TSFlags & SIInstrFlags::Spill;
748 static bool isWWMRegSpillOpcode(uint16_t Opcode) {
749 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
750 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
751 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
752 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
755 static bool isChainCallOpcode(uint64_t Opcode) {
756 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
757 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
764 bool isDPP(uint16_t Opcode) const {
765 return get(Opcode).TSFlags & SIInstrFlags::DPP;
772 bool isTRANS(uint16_t Opcode) const {
773 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
780 bool isVOP3P(uint16_t Opcode) const {
781 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
788 bool isVINTRP(uint16_t Opcode) const {
789 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
796 bool isMAI(uint16_t Opcode) const {
797 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
813 bool isWMMA(uint16_t Opcode) const {
814 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
825 bool isSWMMAC(uint16_t Opcode) const {
826 return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
829 bool isDOT(uint16_t Opcode) const {
830 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
837 bool isLDSDIR(uint16_t Opcode) const {
838 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
845 bool isVINTERP(uint16_t Opcode) const {
846 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
863 static bool sopkIsZext(unsigned Opcode) {
864 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
865 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
866 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
867 Opcode == AMDGPU::S_GETREG_B32;
876 bool isScalarStore(uint16_t Opcode) const {
877 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
884 bool isFixedSize(uint16_t Opcode) const {
885 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
892 bool hasFPClamp(uint16_t Opcode) const {
893 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
912 bool usesFPDPRounding(uint16_t Opcode) const {
913 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
920 bool isFPAtomic(uint16_t Opcode) const {
921 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
931 bool isBarrierStart(unsigned Opcode) const {
932 return Opcode == AMDGPU::S_BARRIER ||
933 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
934 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
935 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
936 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
939 bool isBarrier(unsigned Opcode) const {
940 return isBarrierStart(Opcode) || Opcode == AMDGPU::S_BARRIER_WAIT ||
941 Opcode == AMDGPU::S_BARRIER_INIT_M0 ||
942 Opcode == AMDGPU::S_BARRIER_INIT_IMM ||
943 Opcode == AMDGPU::S_BARRIER_JOIN_IMM ||
944 Opcode == AMDGPU::S_BARRIER_LEAVE ||
945 Opcode == AMDGPU::DS_GWS_INIT ||
946 Opcode == AMDGPU::DS_GWS_BARRIER;
949 static bool isF16PseudoScalarTrans(unsigned Opcode) {
950 return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
951 Opcode == AMDGPU::V_S_LOG_F16_e64 ||
952 Opcode == AMDGPU::V_S_RCP_F16_e64 ||
953 Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
954 Opcode == AMDGPU::V_S_SQRT_F16_e64;
961 bool doesNotReadTiedSource(uint16_t Opcode) const {
962 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
965 static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
966 switch (Opcode) {
984 return Opcode;
988 bool isWaitcnt(unsigned Opcode) const {
989 switch (getNonSoftWaitcntOpcode(Opcode)) {
1107 bool hasVALU32BitEncoding(unsigned Opcode) const;
1116 bool hasModifiers(unsigned Opcode) const;
1152 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
1153 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
1293 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1294 return get(pseudoToMCOpcode(Opcode));
1375 static bool isKillTerminator(unsigned Opcode);
1376 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1400 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1402 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1403 int pseudoToMCOpcode(int Opcode) const;
1495 int getVOPe64(uint16_t Opcode);
1498 int getVOPe32(uint16_t Opcode);
1501 int getSDWAOp(uint16_t Opcode);
1504 int getDPPOp32(uint16_t Opcode);
1507 int getDPPOp64(uint16_t Opcode);
1510 int getBasicFromSDWAOp(uint16_t Opcode);
1513 int getCommuteRev(uint16_t Opcode);
1516 int getCommuteOrig(uint16_t Opcode);
1519 int getAddr64Inst(uint16_t Opcode);
1521 /// Check if \p Opcode is an Addr64 opcode.
1523 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1525 int getIfAddr64Inst(uint16_t Opcode);
1528 int getSOPKOp(uint16_t Opcode);
1530 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1533 int getGlobalSaddrOp(uint16_t Opcode);
1535 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1538 int getGlobalVaddrOp(uint16_t Opcode);
1541 int getVCMPXNoSDstOp(uint16_t Opcode);
1544 /// given an \p Opcode of an SS (SADDR) form.
1546 int getFlatScratchInstSTfromSS(uint16_t Opcode);
1548 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1551 int getFlatScratchInstSVfromSVS(uint16_t Opcode);
1553 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1556 int getFlatScratchInstSSfromSV(uint16_t Opcode);
1558 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1561 int getFlatScratchInstSVfromSS(uint16_t Opcode);
1565 int getMFMAEarlyClobberOp(uint16_t Opcode);
1569 int getVCMPXOpFromVCMP(uint16_t Opcode);