Lines Matching defs:MI
52 void insert(MachineInstr *MI);
71 bool isDeferred(MachineInstr *MI);
107 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
114 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
179 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
186 isCopyInstrImpl(const MachineInstr &MI) const override;
188 bool swapSourceModifiers(MachineInstr &MI,
192 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
234 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
256 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
261 MachineBasicBlock::iterator MI, const DebugLoc &DL,
276 MachineBasicBlock::iterator MI, Register SrcReg,
283 MachineBasicBlock::iterator MI, Register DestReg,
288 bool expandPostRAPseudo(MachineInstr &MI) const override;
290 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
301 expandMovDPP64(MachineInstr &MI) const;
318 inline int commuteOpcode(const MachineInstr &MI) const {
319 return commuteOpcode(MI.getOpcode());
322 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
331 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
380 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
392 static bool isFoldableCopy(const MachineInstr &MI);
394 void removeModOperands(MachineInstr &MI) const;
401 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
404 bool isSchedulingBoundary(const MachineInstr &MI,
408 static bool isSALU(const MachineInstr &MI) {
409 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
416 static bool isVALU(const MachineInstr &MI) {
417 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
424 static bool isImage(const MachineInstr &MI) {
425 return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
432 static bool isVMEM(const MachineInstr &MI) {
433 return isMUBUF(MI) || isMTBUF(MI) || isImage(MI);
440 static bool isSOP1(const MachineInstr &MI) {
441 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
448 static bool isSOP2(const MachineInstr &MI) {
449 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
456 static bool isSOPC(const MachineInstr &MI) {
457 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
464 static bool isSOPK(const MachineInstr &MI) {
465 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
472 static bool isSOPP(const MachineInstr &MI) {
473 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
480 static bool isPacked(const MachineInstr &MI) {
481 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
488 static bool isVOP1(const MachineInstr &MI) {
489 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
496 static bool isVOP2(const MachineInstr &MI) {
497 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
504 static bool isVOP3(const MachineInstr &MI) {
505 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
512 static bool isSDWA(const MachineInstr &MI) {
513 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
520 static bool isVOPC(const MachineInstr &MI) {
521 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
528 static bool isMUBUF(const MachineInstr &MI) {
529 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
536 static bool isMTBUF(const MachineInstr &MI) {
537 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
544 static bool isSMRD(const MachineInstr &MI) {
545 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
552 bool isBufferSMRD(const MachineInstr &MI) const;
554 static bool isDS(const MachineInstr &MI) {
555 return MI.getDesc().TSFlags & SIInstrFlags::DS;
562 static bool isLDSDMA(const MachineInstr &MI) {
563 return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI));
570 static bool isGWS(const MachineInstr &MI) {
571 return MI.getDesc().TSFlags & SIInstrFlags::GWS;
580 static bool isMIMG(const MachineInstr &MI) {
581 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
588 static bool isVIMAGE(const MachineInstr &MI) {
589 return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
596 static bool isVSAMPLE(const MachineInstr &MI) {
597 return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
604 static bool isGather4(const MachineInstr &MI) {
605 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
612 static bool isFLAT(const MachineInstr &MI) {
613 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
618 static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
619 auto Flags = MI.getDesc().TSFlags;
628 static bool isFLATGlobal(const MachineInstr &MI) {
629 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
636 static bool isFLATScratch(const MachineInstr &MI) {
637 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
649 static bool isEXP(const MachineInstr &MI) {
650 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
653 static bool isDualSourceBlendEXP(const MachineInstr &MI) {
654 if (!isEXP(MI))
656 unsigned Target = MI.getOperand(0).getImm();
665 static bool isAtomicNoRet(const MachineInstr &MI) {
666 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
673 static bool isAtomicRet(const MachineInstr &MI) {
674 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
681 static bool isAtomic(const MachineInstr &MI) {
682 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
691 static bool mayWriteLDSThroughDMA(const MachineInstr &MI) {
692 return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
695 static bool isWQM(const MachineInstr &MI) {
696 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
703 static bool isDisableWQM(const MachineInstr &MI) {
704 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
716 static bool isVGPRSpill(const MachineInstr &MI) {
717 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
718 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
719 (isSpill(MI) && isVALU(MI));
728 static bool isSGPRSpill(const MachineInstr &MI) {
729 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
730 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
731 (isSpill(MI) && isSALU(MI));
744 static bool isSpill(const MachineInstr &MI) {
745 return MI.getDesc().TSFlags & SIInstrFlags::Spill;
760 static bool isDPP(const MachineInstr &MI) {
761 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
768 static bool isTRANS(const MachineInstr &MI) {
769 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
776 static bool isVOP3P(const MachineInstr &MI) {
777 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
784 static bool isVINTRP(const MachineInstr &MI) {
785 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
792 static bool isMAI(const MachineInstr &MI) {
793 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
800 static bool isMFMA(const MachineInstr &MI) {
801 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
802 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
805 static bool isDOT(const MachineInstr &MI) {
806 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
809 static bool isWMMA(const MachineInstr &MI) {
810 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
817 static bool isMFMAorWMMA(const MachineInstr &MI) {
818 return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
821 static bool isSWMMAC(const MachineInstr &MI) {
822 return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
833 static bool isLDSDIR(const MachineInstr &MI) {
834 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
841 static bool isVINTERP(const MachineInstr &MI) {
842 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
849 static bool isScalarUnit(const MachineInstr &MI) {
850 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
853 static bool usesVM_CNT(const MachineInstr &MI) {
854 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
857 static bool usesLGKM_CNT(const MachineInstr &MI) {
858 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
872 static bool isScalarStore(const MachineInstr &MI) {
873 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
880 static bool isFixedSize(const MachineInstr &MI) {
881 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
888 static bool hasFPClamp(const MachineInstr &MI) {
889 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
896 static bool hasIntClamp(const MachineInstr &MI) {
897 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
900 uint64_t getClampMask(const MachineInstr &MI) const {
905 return MI.getDesc().TSFlags & ClampFlags;
908 static bool usesFPDPRounding(const MachineInstr &MI) {
909 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
916 static bool isFPAtomic(const MachineInstr &MI) {
917 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
924 static bool isNeverUniform(const MachineInstr &MI) {
925 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
957 static bool doesNotReadTiedSource(const MachineInstr &MI) {
958 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
1011 bool isVGPRCopy(const MachineInstr &MI) const {
1012 assert(isCopyInstr(MI));
1013 Register Dest = MI.getOperand(0).getReg();
1014 const MachineFunction &MF = *MI.getParent()->getParent();
1019 bool hasVGPRUses(const MachineInstr &MI) const {
1020 const MachineFunction &MF = *MI.getParent()->getParent();
1022 return llvm::any_of(MI.explicit_uses(),
1028 static bool modifiesModeRegister(const MachineInstr &MI);
1037 bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
1041 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
1061 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1063 bool isInlineConstant(const MachineInstr &MI,
1066 assert(UseMO.getParent() == &MI);
1068 if (OpIdx >= MI.getDesc().NumOperands)
1071 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
1074 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
1076 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
1077 const MachineOperand &MO = MI.getOperand(OpIdx);
1078 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1081 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1083 if (OpIdx >= MI.getDesc().NumOperands)
1086 if (isCopyInstr(MI)) {
1087 unsigned Size = getOpSize(MI, OpIdx);
1095 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1102 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
1118 bool hasModifiersSet(const MachineInstr &MI,
1120 bool hasAnyModifiersSet(const MachineInstr &MI) const;
1122 bool canShrink(const MachineInstr &MI,
1125 MachineInstr *buildShrunkInst(MachineInstr &MI,
1128 bool verifyInstruction(const MachineInstr &MI,
1131 unsigned getVALUOp(const MachineInstr &MI) const;
1147 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1166 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
1167 const MachineOperand &MO = MI.getOperand(OpNo);
1173 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
1185 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1188 /// for \p MI.
1189 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1205 /// Legalize operands in \p MI by either commuting it or inserting a
1207 void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1209 /// Fix operands in \p MI to satisfy constant bus requirements.
1210 void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1219 void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1220 void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1229 /// instructions and control-flow around \p MI. If present, \p MDT is
1231 /// \returns A new basic block that contains \p MI if new blocks were created.
1233 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1249 MachineBasicBlock::iterator MI) const override;
1251 void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1261 MachineInstr &MI,
1266 static unsigned getNumWaitStates(const MachineInstr &MI);
1268 /// Returns the operand named \p Op. If \p MI does not have an
1271 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1274 const MachineOperand *getNamedOperand(const MachineInstr &MI,
1276 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1280 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1281 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1282 return MI.getOperand(Idx).getImm();
1288 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1297 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1298 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1300 Register isLoadFromStackSlot(const MachineInstr &MI,
1302 Register isStoreToStackSlot(const MachineInstr &MI,
1305 unsigned getInstBundleSize(const MachineInstr &MI) const;
1306 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1308 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1344 bool isBasicBlockPrologue(const MachineInstr &MI,
1414 void fixImplicitOperands(MachineInstr &MI) const;
1416 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1424 const MachineInstr &MI,
1428 getInstructionUniformity(const MachineInstr &MI) const override final;
1431 getGenericInstructionUniformity(const MachineInstr &MI) const;
1446 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1468 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,