Lines Matching defs:VecReg

2349     Register VecReg = MI.getOperand(0).getReg();
2352     assert(VecReg == MI.getOperand(1).getReg());
2356         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2358         .addReg(VecReg, RegState::ImplicitDefine)
2359         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
2381     Register VecReg = MI.getOperand(0).getReg();
2394             .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2396             .addReg(VecReg, RegState::ImplicitDefine)
2397             .addReg(VecReg,
2426     Register VecReg = MI.getOperand(1).getReg();
2438         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
2439         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));