Lines Matching defs:VCC
880 if (DestReg == AMDGPU::VCC) {
882 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
4471 // Set VCC operand with all flags from \p Orig, except for setting it as
4478 (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
4551 return MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
4565 case AMDGPU::VCC:
4826 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
4827 ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
5859 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
7140 Register VCC = RI.getVCC();
7143 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(Opc), VCC)
7145 .addReg(IsSCC ? VCC : CondReg);
7476 // We're just about to add the implicit use / defs of VCC, and we don't want
8421 // SCC must be changed to an instruction that defines VCC. This function makes
8426 // Look for a preceding instruction that either defines VCC or SCC. If VCC
8433 if (MI.modifiesRegister(AMDGPU::VCC, &RI))
8500 // of VCC, but we are still bound by the constant bus requirement to only use
8968 Register UnusedCarry = !RS.isRegUsed(AMDGPU::VCC)
9022 if (Op.isReg() && Op.getReg() == AMDGPU::VCC)