Lines Matching defs:SrcOp

2189     const MachineOperand &SrcOp = MI.getOperand(1);
2191     assert(!SrcOp.isFPImm());
2194       if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
2195           isUInt<32>(SrcOp.getImm()))
2198     if (SrcOp.isImm()) {
2199       APInt Imm(64, SrcOp.getImm());
2222       assert(SrcOp.isReg());
2224           !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
2227           .addReg(SrcOp.getReg())
2229           .addReg(SrcOp.getReg())
2237           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
2240           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
2252     const MachineOperand &SrcOp = MI.getOperand(1);
2253     assert(!SrcOp.isFPImm());
2254     APInt Imm(64, SrcOp.getImm());
2676       const MachineOperand &SrcOp = MI.getOperand(I);
2677       assert(!SrcOp.isFPImm());
2678       if (SrcOp.isImm()) {
2679         APInt Imm(64, SrcOp.getImm());
2683         assert(SrcOp.isReg());
2684         Register Src = SrcOp.getReg();
2688           MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
5328     const MachineOperand &SrcOp = MI.getOperand(1);
5329     if (!SrcOp.isReg() || SrcOp.getReg().isVirtual()) {
9660     const MachineOperand &SrcOp = MI.getOperand(I);
9661     if (!SrcOp.isReg())
9664     Register Reg = SrcOp.getReg();
9665     if (!Reg || !SrcOp.readsReg())
9820     MachineOperand *SrcOp = &Def->getOperand(1);
9821     if (isMask(SrcOp))
9822       SrcOp = &Def->getOperand(2);
9824       SrcOp = &Def->getOperand(1);
9873       .add(*SrcOp)