Lines Matching defs:Src1Idx
2770 unsigned Src1Idx) const {
2778 if (Src0Idx > Src1Idx)
2779 std::swap(Src0Idx, Src1Idx);
2784 static_cast<int>(Src1Idx) &&
2788 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2792 if (isOperandLegal(MI, Src1Idx, &Src0)) {
2795 = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
2803 if (isOperandLegal(MI, Src1Idx, &Src0))
2840 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
2841 if (Src1Idx == -1)
2844 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
4622 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
4628 Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vsrc1X);
4776 for (int OpIdx : {DstIdx, Src0Idx, Src1Idx, Src2Idx}) {
4925 for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx, Src3Idx}) {
4981 for (int OpIdx : {Src0Idx, Src1Idx}) {
5005 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
5027 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
5031 !isInlineConstant(Src1, Desc.operands()[Src1Idx]) &&
5856 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
5857 MachineOperand &Src1 = MI.getOperand(Src1Idx);
5892 legalizeOpWithMove(MI, Src1Idx);
5903 if (isLegalRegOperand(MRI, InstrDesc.operands()[Src1Idx], Src1))
5924 legalizeOpWithMove(MI, Src1Idx);
5934 !isLegalRegOperand(MRI, InstrDesc.operands()[Src1Idx], Src0)) {
5935 legalizeOpWithMove(MI, Src1Idx);
5941 legalizeOpWithMove(MI, Src1Idx);