Lines Matching defs:ResultReg

7518     Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7532     MRI.replaceRegWith(OldDstReg, ResultReg);
7535     addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
7635   Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7644   BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
7648   MRI.replaceRegWith(Dest.getReg(), ResultReg);
7649   addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
8134   Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
8146   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
8148   MRI.replaceRegWith(Dest.getReg(), ResultReg);
8152   addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
8176     Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
8187     BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
8193     MRI.replaceRegWith(Dest.getReg(), ResultReg);
8194     addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
8200   Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
8206   BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
8212   MRI.replaceRegWith(Dest.getReg(), ResultReg);
8213   addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
8310   Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
8330     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32_e64), ResultReg)
8340     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32_e64), ResultReg)
8351     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32_e64), ResultReg)
8365     BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32_e64), ResultReg)
8376   MRI.replaceRegWith(Dest.getReg(), ResultReg);
8377   addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);