Lines Matching defs:NewInstr

7235     MachineInstr *NewInstr = BuildMI(*MBB, &Inst, DL, get(Opc), DestReg)
7241     legalizeOperands(*NewInstr, MDT);
7243     addUsersToMoveToVALUWorklist(NewInstr->getOperand(0).getReg(), MRI,
7297     auto NewInstr =
7302       NewInstr
7309       NewInstr
7313     legalizeOperands(*NewInstr, MDT);
7344     MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
7353     legalizeOperands(*NewInstr, MDT);
7412   auto NewInstr = BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode))
7416     NewInstr->addOperand(Inst.getOperand(0));
7419       NewInstr.addImm(0);
7424         NewInstr.addReg(Src.getReg(), 0, AMDGPU::lo16);
7426         NewInstr->addOperand(Src);
7433       NewInstr.addImm(0);
7434       NewInstr.addImm(Size);
7438       NewInstr.addImm(0);
7449       NewInstr.addImm(Offset);
7450       NewInstr.addImm(BitWidth);
7454         NewInstr.addImm(0);
7456         NewInstr->addOperand(Inst.getOperand(2));
7459         NewInstr.addImm(0);
7461         NewInstr->addOperand(Inst.getOperand(3));
7463         NewInstr.addImm(0);
7465         NewInstr.addImm(0);
7467         NewInstr.addImm(0);
7472       NewInstr->addOperand(Op);
7484         addSCCDefsToVALUWorklist(NewInstr, Worklist);
7489   if (NewInstr->getOperand(0).isReg() && NewInstr->getOperand(0).isDef()) {
7490     Register DstReg = NewInstr->getOperand(0).getReg();
7493     const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*NewInstr);
7498   fixImplicitOperands(*NewInstr);
7500   legalizeOperands(*NewInstr, MDT);