Lines Matching defs:InstDesc

4357   const MCInstrDesc &InstDesc = MI.getDesc();
4358   const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
4379   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
5733   const MCInstrDesc &InstDesc = MI.getDesc();
5734   const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx];
5758             usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {
5763       } else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
5764                  !isInlineConstant(Op, InstDesc.operands()[i])) {
7787   const MCInstrDesc &InstDesc = get(Opcode);
7804   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
7810   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
8021   const MCInstrDesc &InstDesc = get(Opcode);
8050   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
8055   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
8128   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
8144   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
8146   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
8232   const MCInstrDesc &InstDesc = get(Opcode);
8253   BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0);
8255   BuildMI(MBB, MII, DL, InstDesc, MidReg2).add(SrcRegSub1);