Lines Matching defs:EXEC

164         if (!Use.readsRegister(AMDGPU::EXEC, /*TRI=*/nullptr))
186   return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
1738            SrcReg != AMDGPU::EXEC && "exec should not be spilled");
1965            DestReg != AMDGPU::EXEC && "exec should not be spilled");
2277     unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2293     unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
2505     const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4098   // Target-independent instructions do not have an implicit-use of EXEC, even
4099   // when they operate on VGPRs. Treating EXEC modifications as scheduling
4101   return MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
4130   // when executed with an empty EXEC mask.
4133   //       EXEC = 0, but checking for that case here seems not worth it
4154   // However, executing them with EXEC = 0 causes them to operate on undefined
4176     return MI.readsRegister(AMDGPU::EXEC, &RI);
4187   return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
5108     if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
5512     // Insert two move instructions, one to save the original value of EXEC and
5513     // the other to turn on all bits in EXEC. This is required as we can't use
5516     MCRegister Exec = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
5540   MCRegister Exec = isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
6254   if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) &&
6256     Copy.addReg(AMDGPU::EXEC, RegState::Implicit);
6269   unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
6386   // Update EXEC to matching lanes, saving original to SaveExec.
6393   // Update EXEC, switch all done bits to 0 and all todo bits to 1.
6422   unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
6444   // Save the EXEC mask
6505   // Restore the EXEC mask
7141     Register EXEC = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
7144         .addReg(EXEC)
8940                               MI.modifiesRegister(AMDGPU::EXEC, &RI)));
9396     if (I->modifiesRegister(AMDGPU::EXEC, TRI))
9443       // 1. EXEC is only considered const within one BB
9453       } else if (TRI->regsOverlap(Reg, AMDGPU::EXEC))
9488         .addReg(AMDGPU::EXEC, RegState::Implicit);