Lines Matching defs:DestSub1

7809   Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
7810   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
7813     std::swap(DestSub0, DestSub1);
7819     .addReg(DestSub1)
7844   Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7918       BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), DestSub1)
7925       .addReg(DestSub1)
7953   Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
7984       BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L);
7994       .addReg(DestSub1)
8054   Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
8055   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
8063     .addReg(DestSub1)