Lines Matching defs:ScoreBrackets
477 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
518 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
554 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
633 WaitcntBrackets &ScoreBrackets);
719 WaitcntBrackets &ScoreBrackets,
724 MachineBasicBlock &Block, WaitcntBrackets &ScoreBrackets,
727 WaitcntBrackets *ScoreBrackets);
729 WaitcntBrackets &ScoreBrackets);
1186 WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr,
1209 ScoreBrackets.simplifyWaitcnt(OldWait);
1225 ScoreBrackets.simplifyWaitcnt(InstCounterType::STORE_CNT, OldVSCnt);
1241 ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt);
1242 ScoreBrackets.applyWaitcnt(EXP_CNT, Wait.ExpCnt);
1243 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1262 ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt);
1333 WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr,
1366 ScoreBrackets.simplifyWaitcnt(OldWait);
1374 ScoreBrackets.simplifyWaitcnt(OldWait);
1383 ScoreBrackets.simplifyWaitcnt(CT.value(), OldCnt);
1410 ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt);
1411 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1435 ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt);
1436 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1496 ScoreBrackets.applyWaitcnt(CT, NewCnt);
1613 WaitcntBrackets &ScoreBrackets,
1653 ScoreBrackets.getScoreRange(STORE_CNT) != 0 &&
1654 !ScoreBrackets.hasPendingEvent(SCRATCH_WRITE_ACCESS))
1674 if (ScoreBrackets.hasPendingEvent(EXP_GPR_LOCK) ||
1675 ScoreBrackets.hasPendingEvent(EXP_PARAM_ACCESS) ||
1676 ScoreBrackets.hasPendingEvent(EXP_POS_ACCESS) ||
1677 ScoreBrackets.hasPendingEvent(GDS_GPR_LOCK)) {
1693 ScoreBrackets.getRegInterval(&MI, MRI, TRI, CallAddrOpIdx);
1697 ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait);
1703 ScoreBrackets.getRegInterval(&MI, MRI, TRI, RtnAddrOpIdx);
1707 ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait);
1749 const auto &LDSDMAStores = ScoreBrackets.getLDSDMAStores();
1753 ScoreBrackets.determineWait(LOAD_CNT, RegNo + I + 1, Wait);
1758 ScoreBrackets.determineWait(LOAD_CNT, RegNo, Wait);
1760 ScoreBrackets.determineWait(EXP_CNT, RegNo, Wait);
1774 RegInterval Interval = ScoreBrackets.getRegInterval(&MI, MRI, TRI, I);
1784 ScoreBrackets.hasOtherPendingVmemTypes(RegNo,
1787 ScoreBrackets.determineWait(LOAD_CNT, RegNo, Wait);
1788 ScoreBrackets.determineWait(SAMPLE_CNT, RegNo, Wait);
1789 ScoreBrackets.determineWait(BVH_CNT, RegNo, Wait);
1790 ScoreBrackets.clearVgprVmemTypes(RegNo);
1792 if (Op.isDef() || ScoreBrackets.hasPendingEvent(EXP_LDS_ACCESS)) {
1793 ScoreBrackets.determineWait(EXP_CNT, RegNo, Wait);
1795 ScoreBrackets.determineWait(DS_CNT, RegNo, Wait);
1797 ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait);
1817 if (ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
1823 ScoreBrackets.simplifyWaitcnt(Wait);
1842 if (ScoreBrackets.hasPendingEvent(LOAD_CNT))
1844 if (ScoreBrackets.hasPendingEvent(SAMPLE_CNT))
1846 if (ScoreBrackets.hasPendingEvent(BVH_CNT))
1850 return generateWaitcnt(Wait, MI.getIterator(), *MI.getParent(), ScoreBrackets,
1857 WaitcntBrackets &ScoreBrackets,
1865 WCG->applyPreexistingWaitcnt(ScoreBrackets, *OldWaitcntInstr, Wait, It);
1869 ScoreBrackets.applyWaitcnt(Wait);
1982 WaitcntBrackets *ScoreBrackets) {
1991 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_ACCESS, Inst);
1992 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_GPR_LOCK, Inst);
1994 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
2007 ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
2013 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
2023 ScoreBrackets->setPendingFlat();
2026 ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
2031 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst);
2034 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
2038 ScoreBrackets->applyWaitcnt(
2040 ScoreBrackets->setStateOnFunctionEntryOrReturn();
2043 ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt());
2046 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_LDS_ACCESS, Inst);
2049 ScoreBrackets->applyWaitcnt(EXP_CNT, Imm);
2053 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst);
2055 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst);
2057 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst);
2064 ScoreBrackets->updateByEvent(TII, TRI, MRI, SQ_MESSAGE, Inst);
2073 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
2155 WaitcntBrackets &ScoreBrackets) {
2160 ScoreBrackets.dump();
2195 isPreheaderToFlush(Block, ScoreBrackets);
2198 Modified |= generateWaitcntInstBefore(Inst, ScoreBrackets, OldWaitcntInstr,
2221 ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
2247 updateEventWaitcntAfter(Inst, &ScoreBrackets);
2252 ScoreBrackets.simplifyWaitcnt(Wait);
2254 ScoreBrackets, /*OldWaitcntInstr=*/nullptr);
2259 ScoreBrackets.dump();
2283 isPreheaderToFlush(Block, ScoreBrackets)) {
2284 if (ScoreBrackets.hasPendingEvent(LOAD_CNT))
2286 if (ScoreBrackets.hasPendingEvent(SAMPLE_CNT))
2288 if (ScoreBrackets.hasPendingEvent(BVH_CNT))
2293 Modified |= generateWaitcnt(Wait, Block.instr_end(), Block, ScoreBrackets,
2302 WaitcntBrackets &ScoreBrackets) {
2316 shouldFlushVmCnt(Loop, ScoreBrackets)) {