Lines Matching defs:getSubtarget

961 const GCNSubtarget *SITargetLowering::getSubtarget() const {
1682     unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
2484   if (UserSGPRInfo.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
2508       MF.getSubtarget<GCNSubtarget>().getExplicitKernelArgOffset();
2669   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2763   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2799   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3078         = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
3542   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
4347   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4398   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4418   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4468   const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4556   const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4961   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4967     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MIN_U32);
4969     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_U32);
4994     const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5043     const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5126     const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5219     assert(MF->getSubtarget<GCNSubtarget>().hasShaderCyclesHiLoRegisters());
5268     return emitIndirectSrc(MI, *BB, *getSubtarget());
5279     return emitIndirectDst(MI, *BB, *getSubtarget());
5285     const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5345     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
5362     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
5392       const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5422     if (getSubtarget()->hasGWSAutoReplay()) {
5446     if (getSubtarget()->hasDenormModeInst()) {
6037   unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
6067   unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
6654   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
7901   const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
8409     if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
8556     return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
9521     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
10014   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
11410   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
11529     if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
11641   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
12321   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
13135     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
13369       EltSize, NumElem, Idx->isDivergent(), getSubtarget());
14715     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15043   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15120   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15215   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15290   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15673   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
15748           DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
15776   Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
15795       knownBitsForWorkitemID(*getSubtarget(), KB, Known, 0);
15798       knownBitsForWorkitemID(*getSubtarget(), KB, Known, 1);
15801       knownBitsForWorkitemID(*getSubtarget(), KB, Known, 2);
15807       Known.Zero.setHighBits(Size - getSubtarget()->getWavefrontSizeLog2());
15815           llvm::countl_zero(getSubtarget()->getAddressableLocalMemorySize()));
15875   if (!ML || DisableLoopAlignment || !getSubtarget()->hasInstPrefetch() ||
15876       getSubtarget()->hasInstFwdPrefetchBug())
15889   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();