Lines Matching defs:N0
9964 SDValue N0 = Offset;
9967 if ((C1 = dyn_cast<ConstantSDNode>(N0)))
9968 N0 = SDValue();
9969 else if (DAG.isBaseWithConstantOffset(N0)) {
9970 C1 = cast<ConstantSDNode>(N0.getOperand(1));
9971 N0 = N0.getOperand(0);
9993 if (!N0)
9994 N0 = OverflowVal;
9996 SDValue Ops[] = { N0, OverflowVal };
9997 N0 = DAG.getNode(ISD::ADD, DL, MVT::i32, Ops);
10001 if (!N0)
10002 N0 = DAG.getConstant(0, DL, MVT::i32);
10005 return {N0, SDValue(C1, 0)};
10027 SDValue N0 = CombinedOffset.getOperand(0);
10033 Offsets[0] = N0;
11306 SDValue N0 = N->getOperand(0);
11311 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
11312 N0->hasOneUse())
11319 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11325 if (N0->getOpcode() == ISD::OR &&
11326 !DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1)))
11343 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
11348 (N0.getOpcode() == ISD::OR ||
11349 N0->getFlags().hasNoUnsignedWrap()));
12573 SDValue N0 = N->getOperand(0);
12575 if (N0.isUndef()) {
12581 if (VT == MVT::f32 && (N0.getOpcode() == ISD::UINT_TO_FP ||
12582 N0.getOpcode() == ISD::SINT_TO_FP)) {
12583 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
12588 if ((VT == MVT::f16 && N0.getOpcode() == ISD::FSQRT) &&
12589 N->getFlags().hasAllowContract() && N0->getFlags().hasAllowContract()) {
12591 N0.getOperand(0), N->getFlags());
12957 SDValue N0 = N->getOperand(0);
12961 if (N0.isUndef()) {
12966 if (ConstantFPSDNode *CFP = isConstOrConstSplatFP(N0)) {
12978 if (N0.getOpcode() == ISD::BUILD_VECTOR && VT == MVT::v2f16 &&
12982 SDValue Lo = N0.getOperand(0);
12983 SDValue Hi = N0.getOperand(1);
12988 SDValue Op = N0.getOperand(I);
13584 const SDNode *N0,
13586 EVT VT = N0->getValueType(0);
13599 (N0->getFlags().hasAllowContract() &&
13647 SDValue N0, SDValue N1, SDValue N2,
13651 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2);
16449 bool SITargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,
16451 if (!N0.hasOneUse())
16453 // Take care of the opportunity to keep N0 uniform
16454 if (N0->isDivergent() || !N1->isDivergent())
16458 return (DAG.isBaseWithConstantOffset(N0) &&
16459 hasMemSDNodeUser(*N0->use_begin()));
16463 Register N0, Register N1) const {
16464 return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks