Lines Matching defs:DCI
7287 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
7293 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
10174 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {
10175 SelectionDAG &DAG = DCI.DAG;
10190 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) ||
10228 DCI.AddToWorklist(Cvt.getNode());
10233 DCI.AddToWorklist(Cvt.getNode());
11209 DAGCombinerInfo &DCI) const {
11215 SelectionDAG &DAG = DCI.DAG;
11225 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
11228 DCI.AddToWorklist(Cvt.getNode());
11243 DAGCombinerInfo &DCI) const {
11246 SelectionDAG &DAG = DCI.DAG;
11305 DAGCombinerInfo &DCI) const {
11323 SelectionDAG &DAG = DCI.DAG;
11332 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext());
11337 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace))
11369 DAGCombinerInfo &DCI) const {
11370 SelectionDAG &DAG = DCI.DAG;
11379 N->getMemoryVT(), DCI);
11403 DAGCombinerInfo &DCI,
11418 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi);
11505 DAGCombinerInfo &DCI) const {
11506 if (DCI.isBeforeLegalize())
11509 SelectionDAG &DAG = DCI.DAG;
11518 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
12183 static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
12184 SelectionDAG &DAG = DCI.DAG;
12275 DAGCombinerInfo &DCI) const {
12276 SelectionDAG &DAG = DCI.DAG;
12387 if (SDValue Perm = matchPERM(N, DCI))
12392 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
12413 DCI.AddToWorklist(LowOr.getNode());
12414 DCI.AddToWorklist(HiBits.getNode());
12425 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR,
12434 DAGCombinerInfo &DCI) const {
12435 if (SDValue RV = reassociateScalarOps(N, DCI.DAG))
12442 SelectionDAG &DAG = DCI.DAG;
12447 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
12476 DAGCombinerInfo &DCI) const {
12478 DCI.getDAGCombineLevel() < AfterLegalizeDAG)
12494 DAGCombinerInfo &DCI) const {
12512 SDVTList ResList = DCI.DAG.getVTList(MVT::i32);
12519 SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode(
12521 SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad);
12541 SDVTList ResList = DCI.DAG.getVTList(MVT::i32,
12545 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N),
12549 return DCI.DAG.getMergeValues({BufferLoadSignExt,
12556 DAGCombinerInfo &DCI) const {
12557 SelectionDAG &DAG = DCI.DAG;
12571 DAGCombinerInfo &DCI) const {
12576 return DCI.DAG.getConstantFP(
12583 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
12590 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT,
12594 return AMDGPUTargetLowering::performRcpCombine(N, DCI);
12955 DAGCombinerInfo &DCI) const {
12956 SelectionDAG &DAG = DCI.DAG;
13175 DAGCombinerInfo &DCI) const {
13176 SelectionDAG &DAG = DCI.DAG;
13267 DAGCombinerInfo &DCI) const {
13272 SelectionDAG &DAG = DCI.DAG;
13311 DAGCombinerInfo &DCI) const {
13315 return DCI.DAG.getUNDEF(N->getValueType(0));
13373 SDNode *N, DAGCombinerInfo &DCI) const {
13375 SelectionDAG &DAG = DCI.DAG;
13398 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) {
13426 DCI.AddToWorklist(Elt0.getNode());
13427 DCI.AddToWorklist(Elt1.getNode());
13449 if (!DCI.isBeforeLegalize())
13466 DCI.AddToWorklist(Cast.getNode());
13470 DCI.AddToWorklist(Elt.getNode());
13473 DCI.AddToWorklist(Srl.getNode());
13477 DCI.AddToWorklist(Trunc.getNode());
13492 DAGCombinerInfo &DCI) const {
13503 SelectionDAG &DAG = DCI.DAG;
13539 DAGCombinerInfo &DCI) const {
13552 SelectionDAG &DAG = DCI.DAG;
13664 DAGCombinerInfo &DCI) const {
13667 SelectionDAG &DAG = DCI.DAG;
14041 DAGCombinerInfo &DCI) const {
14042 SelectionDAG &DAG = DCI.DAG;
14050 if (SDValue Folded = tryFoldToMad64_32(N, DCI))
14201 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
14239 DAGCombinerInfo &DCI) const {
14240 SelectionDAG &DAG = DCI.DAG;
14281 DAGCombinerInfo &DCI) const {
14289 SelectionDAG &DAG = DCI.DAG;
14305 DAGCombinerInfo &DCI) const {
14306 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
14309 SelectionDAG &DAG = DCI.DAG;
14347 DAGCombinerInfo &DCI) const {
14348 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
14351 SelectionDAG &DAG = DCI.DAG;
14394 DAGCombinerInfo &DCI) const {
14395 SelectionDAG &DAG = DCI.DAG;
14429 DAGCombinerInfo &DCI) const {
14430 SelectionDAG &DAG = DCI.DAG;
14504 DAGCombinerInfo &DCI) const {
14505 SelectionDAG &DAG = DCI.DAG;
14600 DAGCombinerInfo &DCI) const {
14601 SelectionDAG &DAG = DCI.DAG;
14637 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) {
14641 DCI.AddToWorklist(N);
14654 DAGCombinerInfo &DCI) const {
14659 const MachineFunction &MF = DCI.DAG.getMachineFunction();
14664 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0));
14669 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
14676 DAGCombinerInfo &DCI) const {
14681 return performAddCombine(N, DCI);
14683 return performSubCombine(N, DCI);
14686 return performAddCarrySubCarryCombine(N, DCI);
14688 return performFAddCombine(N, DCI);
14690 return performFSubCombine(N, DCI);
14692 return performFDivCombine(N, DCI);
14694 return performSetCCCombine(N, DCI);
14707 return performMinMaxCombine(N, DCI);
14709 return performFMACombine(N, DCI);
14711 return performAndCombine(N, DCI);
14713 return performOrCombine(N, DCI);
14718 return matchPERM(N, DCI);
14723 return performXorCombine(N, DCI);
14725 return performZeroExtendCombine(N, DCI);
14727 return performSignExtendInRegCombine(N , DCI);
14729 return performClassCombine(N, DCI);
14731 return performFCanonicalizeCombine(N, DCI);
14733 return performRcpCombine(N, DCI);
14748 return performUCharToFloatCombine(N, DCI);
14750 return performFCopySignCombine(N, DCI);
14755 return performCvtF32UByteNCombine(N, DCI);
14757 return performFMed3Combine(N, DCI);
14759 return performCvtPkRTZCombine(N, DCI);
14761 return performClampCombine(N, DCI);
14763 SelectionDAG &DAG = DCI.DAG;
14781 return performExtractVectorEltCombine(N, DCI);
14783 return performInsertVectorEltCombine(N, DCI);
14785 return performFPRoundCombine(N, DCI);
14787 if (SDValue Widened = widenLoad(cast<LoadSDNode>(N), DCI))
14792 if (!DCI.isBeforeLegalize()) {
14794 return performMemSDNodeCombine(MemNode, DCI);
14801 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);