Lines Matching defs:CCInfo

74 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
77     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
2241 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
2252     CCInfo.AllocateReg(Reg);
2267       CCInfo.AllocateReg(Reg);
2281       CCInfo.AllocateReg(Reg);
2291 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
2297   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
2300     int64_t Offset = CCInfo.AllocateStack(4, Align(4));
2306   Reg = CCInfo.AllocateReg(Reg);
2309   MachineFunction &MF = CCInfo.getMachineFunction();
2315 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
2319   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
2324   Reg = CCInfo.AllocateReg(Reg);
2327   MachineFunction &MF = CCInfo.getMachineFunction();
2333 // CCInfo state. Technically we could get away with this for values passed
2335 static void allocateFixedSGPRInputImpl(CCState &CCInfo,
2338   Reg = CCInfo.AllocateReg(Reg);
2340   MachineFunction &MF = CCInfo.getMachineFunction();
2344 static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {
2346     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,
2349     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
2352 static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {
2354     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,
2357     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
2363   CCState &CCInfo, MachineFunction &MF,
2369     Arg = allocateVGPR32Input(CCInfo, Mask);
2374     Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
2379     Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
2384   CCState &CCInfo, MachineFunction &MF,
2386   Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
2397   CCState &CCInfo,
2406     allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);
2411     allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
2416     allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);
2419     allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);
2424     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);
2427     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);
2430     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);
2433     allocateSGPR32Input(CCInfo, ArgInfo.LDSKernelId);
2437 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
2445     CCInfo.AllocateReg(ImplicitBufferPtrReg);
2452     CCInfo.AllocateReg(PrivateSegmentBufferReg);
2458     CCInfo.AllocateReg(DispatchPtrReg);
2466     CCInfo.AllocateReg(QueuePtrReg);
2472     CCInfo.AllocateReg(InputPtrReg);
2481     CCInfo.AllocateReg(DispatchIDReg);
2487     CCInfo.AllocateReg(FlatScratchInitReg);
2493     CCInfo.AllocateReg(PrivateSegmentSizeReg);
2503     CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,
2561         CCInfo.AllocateReg(Reg);
2569 void SITargetLowering::allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
2576     CCInfo.AllocateReg(Reg);
2581 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
2606       CCInfo.AllocateReg(Reg);
2614       CCInfo.AllocateReg(Reg);
2620       CCInfo.AllocateReg(Reg);
2626       CCInfo.AllocateReg(Reg);
2633     CCInfo.AllocateReg(Reg);
2647         PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
2654     CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
2816   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2857       CCInfo.AllocateReg(AMDGPU::VGPR0);
2858       CCInfo.AllocateReg(AMDGPU::VGPR1);
2883     analyzeFormalArgumentsCompute(CCInfo, Ins);
2886     allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2887     allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2889       allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, Ins, MF, *TRI, *Info);
2891     allocateLDSKernelId(CCInfo, MF, *TRI, *Info);
2894     allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
2898       CCInfo.AllocateReg(Info->getScratchRSrcReg());
2900     allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2905     CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
3114     allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
3123   unsigned StackArgSize = CCInfo.getStackSize();
3144   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3145   if (!CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)))
3152     if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))
3182   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3186   CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3262   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3264   CCInfo.AnalyzeCallResult(Ins, RetCC);
3312     CCState &CCInfo,
3405       if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
3409           CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));
3497     CCInfo.AllocateReg(OutgoingArg->getRegister());
3499     unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));
3587   CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
3589   CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
3595   if (CCInfo.getStackSize() > FuncInfo->getBytesInStackArgArea())
3704   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3709     passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3712   CCInfo.AnalyzeCallOperands(Outs, AssignFn);
3715   unsigned NumBytes = CCInfo.getStackSize();