Lines Matching defs:TRI
80 const SIRegisterInfo *TRI = ST.getRegisterInfo();
81 unsigned Size = TRI->getSpillSize(RC);
82 Align Alignment = TRI->getSpillAlign(RC);
97 if (TRI->spillSGPRToVGPR() &&
107 dbgs() << printReg(SGPR, TRI) << " requires fallback spill to "
108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane
119 << printReg(SGPR, TRI) << '\n');
126 LLVM_DEBUG(dbgs() << "Saving " << printReg(SGPR, TRI) << " with copy to "
127 << printReg(ScratchSGPR, TRI) << '\n');
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI,
151 TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, IsKill, FrameReg,
158 const SIRegisterInfo &TRI,
173 TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, false, FrameReg,
182 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0);
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1);
202 static void initLiveUnits(LiveRegUnits &LiveUnits, const SIRegisterInfo &TRI,
207 LiveUnits.init(TRI);
232 const SIRegisterInfo &TRI;
246 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ true);
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
260 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR,
277 : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
295 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ false);
304 : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
306 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL,
323 : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
342 const SIRegisterInfo &TRI,
346 FuncInfo(MF.getInfo<SIMachineFunctionInfo>()), TII(TII), TRI(TRI),
349 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);
350 SplitParts = TRI.getRegSplitParts(RC, EltSize);
387 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
406 LiveUnits.init(*TRI);
412 ArrayRef<MCPhysReg> AllSGPR64s = TRI->getAllSGPR64(MF);
419 MRI.isAllocatable(Reg) && !TRI->isSubRegisterEq(Reg, GITPtrLoReg)) {
426 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0);
427 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1);
465 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
466 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
542 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
555 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
568 ArrayRef<MCPhysReg> AllSGPR128s = TRI->getAllSGPR128(MF);
579 (!GITPtrLoReg || !TRI->isSubRegisterEq(Reg, GITPtrLoReg))) {
582 MRI.reserveReg(Reg, TRI);
612 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
667 TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {
668 ArrayRef<MCPhysReg> AllSGPRs = TRI->getAllSGPR32(MF);
675 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {
736 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
743 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
744 Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
784 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
785 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
791 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
819 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
820 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
856 Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
857 Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
897 const SIRegisterInfo &TRI = TII->getRegisterInfo();
900 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, IsProlog);
903 MRI, LiveUnits, *TRI.getWaveMaskRegClass());
928 const SIRegisterInfo &TRI = TII->getRegisterInfo();
946 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL,
955 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1);
967 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), TRI.getExec())
984 PrologEpilogSGPRSpillBuilder SB(Reg, Spill.second, MBB, MBBI, DL, TII, TRI,
1014 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1028 PrologEpilogSGPRSpillBuilder SB(Reg, Spill.second, MBB, MBBI, DL, TII, TRI,
1049 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL,
1058 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1);
1070 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), TRI.getExec())
1086 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1092 TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register();
1117 if (TRI.hasStackRealignment(MF))
1131 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ true);
1139 DL, TII, TRI, LiveUnits, FramePtrReg);
1161 LiveUnits.init(TRI);
1195 if ((HasBP = TRI.hasBasePointer(MF))) {
1235 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1267 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ false);
1340 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1351 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
1352 FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC),
1353 TRI->getSpillAlign(*RC));
1382 TRI->isAGPR(MRI, VReg))) {
1386 TRI->eliminateFrameIndex(MI, 0, FIOp, RS);
1442 RS->addScavengingFrameIndex(FuncInfo->getScavengeFI(MFI, *TRI));
1456 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1467 TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
1468 if (UnusedLowVGPR && (TRI->getHWRegIndex(UnusedLowVGPR) <
1469 TRI->getHWRegIndex(VGPRForAGPRCopy))) {
1475 MRI.reserveReg(UnusedLowVGPR, TRI);
1482 TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_64RegClass, MF);
1489 MRI.reserveReg(UnusedLowSGPR, TRI);
1502 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1504 LiveUnits.init(*TRI);
1511 const TargetRegisterClass &RC = *TRI->getWaveMaskRegClass();
1517 MRI.reserveReg(ReservedRegForExecCopy, TRI);
1557 if (TRI->hasBasePointer(MF)) {
1558 Register BasePtrReg = TRI->getBaseRegister();
1584 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1628 SavedVGPRs.clearBitsNotInMask(TRI->getAllVectorRegMask());
1634 SavedVGPRs.clearBitsInMask(TRI->getAllAGPRRegMask());
1661 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1667 SavedRegs.clearBitsInMask(TRI->getAllVectorRegMask());
1689 Register RetAddrReg = TRI->getReturnAddressReg(MF);
1692 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub0));
1693 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub1));
1698 MachineFunction &MF, const TargetRegisterInfo *TRI,