Lines Matching defs:ScratchRsrcReg

548   Register ScratchRsrcReg = MFI->getScratchRSrcReg();
550   if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&
555       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
556     return ScratchRsrcReg;
580       MRI.replaceRegWith(ScratchRsrcReg, Reg);
587   return ScratchRsrcReg;
628   Register ScratchRsrcReg;
630     ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);
633   if (ScratchRsrcReg) {
636         OtherBB.addLiveIn(ScratchRsrcReg);
647     if (ScratchRsrcReg && PreloadedScratchRsrcReg) {
667       TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {
675           !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {
711   if ((NeedsFlatScratchInit || ScratchRsrcReg) &&
721   if (ScratchRsrcReg) {
724                                          ScratchRsrcReg, ScratchWaveOffsetReg);
728 // Emit scratch RSRC setup code, assuming `ScratchRsrcReg != AMDGPU::NoReg`
732     Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {
743     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
744     Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
760     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
764       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
784     Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
785     Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
791       Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
798           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
813           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
819       Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
820       Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
824         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
828         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
833       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
837       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
841     if (ScratchRsrcReg != PreloadedScratchRsrcReg) {
842       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
856   Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
857   Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
864       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
868       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);