Lines Matching defs:Def
660 MachineInstr *Def = MRI->getVRegDef(UseReg);
661 if (!Def || !Def->isRegSequence())
664 for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {
665 MachineOperand *Sub = &Def->getOperand(I);
683 Defs.emplace_back(Sub, Def->getOperand(I + 1).getImm());
717 MachineInstr *Def = MRI->getVRegDef(UseReg);
719 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) {
720 MachineOperand &DefOp = Def->getOperand(1);
922 MachineOperand *Def = Defs[I].first;
924 if (Def->isImm() &&
925 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
926 int64_t Imm = Def->getImm();
932 } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
933 auto Src = getRegSubRegPair(*Def);
934 Def->setIsKill(false);
941 B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
945 assert(Def->isReg());
946 Def->setIsKill(false);
947 auto Src = getRegSubRegPair(*Def);
956 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
967 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
1196 MachineInstr *Def = MRI->getVRegDef(Op.getReg());
1197 if (Def && Def->isMoveImmediate()) {
1198 MachineOperand &ImmSrc = Def->getOperand(1);
1567 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
1570 if (TII->getClampMask(*Def) != TII->getClampMask(MI))
1573 if (Def->mayRaiseFPException())
1576 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
1580 LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def);
1585 Register DefReg = Def->getOperand(0).getReg();
1601 if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
1602 Def->eraseFromParent();
1744 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
1745 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
1749 if (Def->mayRaiseFPException())
1754 if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))
1757 LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def);
1760 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1766 if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
1767 Def->eraseFromParent();
1824 for (auto &[Def, SubIdx] : Defs) {
1825 Def->setIsKill(false);
1826 if (TRI->isAGPR(*MRI, Def->getReg())) {
1827 RS.add(*Def);
1829 MachineInstr *SubDef = MRI->getVRegDef(Def->getReg());
1831 RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());
1967 if (MachineInstr *Def = MRI->getVRegDef(Reg)) {
1971 if (Def->isCopy()) {
1974 if (isAGPRCopy(*TRI, *MRI, *Def, AGPRSrc, AGPRSubReg)) {
1986 MachineOperand &CopyIn = Def->getOperand(1);
1992 InsertMBB = Def->getParent();
1993 InsertPt = InsertMBB->SkipPHIsLabelsAndDebug(++Def->getIterator());
2030 MachineOperand &Def = MI.getOperand(0);
2031 if (!Def.isDef())
2034 Register DefReg = Def.getReg();
2065 if (!TII->isOperandLegal(MI, 0, &Def)) {
2145 MachineInstr *Def = MRI->getVRegDef(Reg);
2146 MachineBasicBlock *DefMBB = Def->getParent();
2154 BuildMI(*DefMBB, ++Def->getIterator(), Def->getDebugLoc(),
2160 BuildMI(*DefMBB, ++VGPRCopy->getIterator(), Def->getDebugLoc(),